PDSP16488AMA Datasheet, PDF (5/30 Pages) Mitel Networks Corporation – Single Chip 2D Convolver with Integral Line Delays

LINE N-1
3 X 3 WINDOW
C4 C5 C6
LINE N C8 C9 C10
LINE N+1
C0 C1 C2
5 X 5 WINDOW
LINE N-2 _{C48 C49 C50 C51 C52}
LINE N-1 C8 C9 C10 C11 C12
LINE N _{C40 C41 C42 C43} C44
LINE N+1
C0
C1 C2 C3 C4
LINE N+2 ^{C32 C33 C34 C35 C36}
PDSP16488A MA
IP7:0
FIELD
DELAY
VIDEO
LINE N+2
1024
ODD
FIELD
L7:0
1024
1024
N+1
N-1
4X4
OR
8X4
N
ARRAY
Output is shifted
by 1 line in
every field
1024
IP7:0
FIELD
DELAY
512
ODD
N+1
FIELD
512
N-1
512
VIDEO
L7:0
LINE N+2
*_{Delay is By-Passed}
[REG B,BIT 7 IS SET]
512
512
*
Output is shifted
8X8
ARRAY
by 1 line in
N+2
every field
512
N
512
N-2
512
LINE N-3
LINE N-2
LINE N-1
LINE N
LINE N+1
LINE N+2
LINE N+3
LINE N+4
8 X 8 WINDOW
C24 C25 C26 C27 C28 C29 C30 C31
C56 C57 C58 C59 C60 C61 C62 C63
C16 C17 C18 C19 C20 C21 C22 C23
FIELD
DELAY
IP7:0
512
ODD
FIELD
512
512
C48 C49 C50 C51 C52 C53 C54 C55
C8 C9
C10 C11 C12 C13 C14 C15
VIDEO
LINE N+4
C40 C41 C42 C43 C44 C45 C46 C47
512
L7:0
512
512
C0 C1 C2 C3
C4 C5 C6
C7
*_{Delay is By-Passed}
512
[REG B,BIT 7 IS SET]
512
C32 C33 C34 C35 C36 C37 C38 C39
N+3
N+1
N-1
N-3
* ^8X8
N+4 ^ARRAY
N+2
N
N-2
Output is shifted
by 2 lines in
every field
Figure 3. Line Delay Allocations in Single Device Interlaced Systems
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