PDSP16488AMA Datasheet, PDF (2/30 Pages) Mitel Networks Corporation – Single Chip 2D Convolver with Integral Line Delays

PDSP16488A MA
CE DS R/W PC0 PC1 RSE CS3:0
MULTI PURPOSE
DATA BUS
X15:0
PROG
MASTER
SINGLE
DELOP
IP7:0
BY
PASS
L7:0
CONTROL
X
DELAY
Y
DELAY
1
LINE
DELAY
Y
DELAY
3
LINE
DLYS
4
LINE
DLYS
COEFFICIENT
STORE (64)
8X8
ARRAY OF
MAC'S
CONTROL
REGISTERS
COMPARATOR
CLOCK
Fig. 2 Functional Block Diagram
BIN
OVER
FLOW
D15:0
DATA
OUT
OEN
PIN NO
AC PACKAGE
FUNCTION
A1
L0
B1
F1
C2
L1
C1
L2
D2
L3
D1
SPARE
E2
L4
E1
L5
F2
L6
G2
L7
G1
IP7
H2
SPARE
J1
IP6
J2
IP5
K1
IP4
K2
SPARE
L1
IP3
L2
IP2
M1
IP1
N1
IP0
N2
BYPASS
2
PIN NO
AC PACKAGE
M3
N3
M4
N4
M5
N5
M6
M7
N7
M8
N9
M9
N10
M10
N11
M11
N12
N13
M13
L12
L13
FUNCTION
X15
X14
X13
SPARE
SINGLE
X12
X11
MASTER
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0
DELOP
PC0
PIN NO
AC PACKAGE
K12
K13
J12
J13
H12
G12
G13
F12
E13
E12
D13
D12
C13
C12
B13
A13
A12
B11
A11
B10
A10
FUNCTION
RES
CS0
CS1
CS2
CS3
PROG
DS
CE
R/W
HRES
OV
PC1
BIN
OEN
D0
D1
D2
D3
D4
D5
D6
Pin out Table (84 pin PGA - AC84)
PIN NO
AC PACKAGE
FUNCTION
B9
D7
A9
D8
B8
CLK
B7
SPARE
A7
D9
B6
D10
A5
D11
B5
SPARE
A4
D12
B4
D13
A3
D14
B3
D15
A2
F0
F1
VDD
N6
VDD
F13
VDD
A6
VDD
H1
GND
N8
GND
H13
GND
A8
GND