PDSP16488AMA Datasheet, PDF (18/30 Pages) Mitel Networks Corporation – Single Chip 2D Convolver with Integral Line Delays

PDSP16488A MA
APPLICATIONS INFORMATION
DEVICE REQUIREMENTS
The number of devices required to implement a given
convolver window depends on the size of the window, the
required pixel rate, and whether the pixel accuracy is to be 8
or 16 bits. In practice the PDSP16488A supports windows
requiring one, two, four, six, or eight devices without addi-
tional logic. Table 2 gives typical window sizes which may be
obtained with the above number of devices.
Figures 11 through 18 show system interconnections
for these arrangements. Other configurations are possible but
may need the support of additional pixel/line delays and/or
expansion adders. Although not necessarily shown, all con-
figurations can be supported by either an EPROM or a Host
Computer . Interlaced or non-interlaced video may also be
used, unless explicitly stated otherwise in the text.
Expansion with 8 bit pixels is a straightforward process
and the number of devices needed is easily deduced from the
window sizes available in a single device. At pixel rates above
20MHz it may not be practical to use more than four devices.
since the full 32 bit intermediate precision is not available. The
lack of expansion multiplexing reduces the intermediate pre-
cision to 16 bits. The partial sum outputs must thus not
overflow these 16 bits; this will require the coefficients to be
scaled down appropriately with a resulting loss in accuracy.
Expansion with 16 bit pixels can be achieved in several
ways. The simplest way is to use two devices, each working
with 8 bit pixels. One device handles the least significant part
of the data, and its output feeds the expansion input of a
second device. This performs the most significant half of the
calculation. The least significant half is then added to the most
significant sum, after the latter has been multiplied by 256 ie
shifted by eight places. This shift is done internally and
controlled by Register D, bit 1. The internal 32 bit accuracy
prevents any loss in precision due the shift and add operation.
The window size with this arrangement is restricted to
that available in a single device, at the required pixel rate but
with 8 bit pixels. Thus two devices can be used , for example,
to provide an 8 x 8 window with 16 bit pixels and 10 MHz rates.
If a larger extended precision window is needed, it is
possible to use four devices. Each device is then programmed
to be in a 16 bit data mode, but should be restricted to rates
below 20 MHz, if the 32 bit intermediate precision is to be
maintained. In the 16 bit modes, however, the output from the
last line delay is not available due to pin limitations. This is not
a problem in a four device interlaced system, since half of the
devices will be fed from an external field delay. In non
interlaced systems additional external line delays would be
needed. An alternative approach would be to configure all the
devices in the appropriate 8 bit mode, do separate least
significant and most significant calculations, and then com-
bine the results in an external adder after a wired in shift.
SINGLE DEVICE SYSTEMS
Figures 11 illustrates both EPROM and Host sup-
ported single device systems, with or without interlaced video.
In both cases the SINGLE and X15 pins must be tied tied low,
and the PC0, PC1, and DS pins are redundant. The PROG pin
becomes an output and indicates that a register load se-
quence is occuring. The first line delay must always be
bypassed in a non interlaced system, however, since an
internal pull up is not provided, the BYPASS pin should be tied
to VCC for the correct operation. With interlaced video the
BYPASS input is used to distinguish between the odd and
even fields.
The CE input may be left open circuit if coefficients are
to be simply loaded after a power on reset signal; the latter
being applied to the RES input. Alternatively the CE input may
be used to change the coefficients at any time after power on
reset; the EPROM would then need additional address bits for
the extra sets of coefficients that are to be stored.
In an interlaced system the pixels from the previous
field must use the IP7:0 inputs, and the live pixels must use the
L7:0 inputs. Interlaced sysytems requiring extended precision
pixels are non supported with a single device, since the L7:0
inputs are then use for the least significant 8 bits, and the IP7:0
inputs for any more significant bits.
If the X15 pin is left open circuit, an internal pull up will
configure the device in the host supported mode. The host
must then supply a data strobe and a R/W control line. The
X7:0 pins must be connected to the host data bus, and are
used to both load and read back register values. The PROG
and CE pins may be connected together, and then driven by
a host address decode. The output on PC1, which provides a
REPLY to the host, need not be used if the width of the data
strobe is greater than the maximum TEXP value given in
Figure 7.
The configuration bits 6:4 in REGISTER A define the
window size, maximum pixel rate, and pixel resolution. Win-
dow sizes smaller than the maximum in any configuration are
implemented by filling in the window with `zero' coefficients.
Bits 3:0 are irrelevent in the SINGLE mode, as is bit 7 if the gain
contol is used.
The result would be expected to lie in either the bottom 20
bits of the 32 bit result , or possibly in the next 20 bit field
displaced by four bits. Register C, bits 5:4, must thus select
one of these fields for subsequent use by the gain control. The
gain is then adjusted such that the 16 outputs available on
pins are in fact the 16 most significant bits of the result. The
gain needed is application specific, but if too much gain is used
the OV pin will indicate an overflow.
Register B, bits 2:1, must be set to select the required
method of defining the length of the line delays, and the use
of bit 3 is dependent on any external pixel delays before the
convolver input. No additional delays are needed on the pixel
inputs in a single device system, and REGISTER D, bits 4:2,
should be reset. The pipeline delay in the DELOP output path
should match one of those in Table 4, and is window size
dependent.
DUAL DEVICE CONFIGURATIONS
Two devices, each configured with 8 bit pixels and 8W
x 4D windows, can be used to provide an 8 x 8 window at up
to 20 MHz pixel rates. Figure 12 shows both the non interlaced
and interlaced arrangements.
Video lines containing up to 1024 pixels are possible
in both configurations, since each device only needs four line
delays. One device is configured as the MASTER by ground-
ing the MASTER pin; the other then receives control signals in
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