PDSP16488AMA Datasheet, PDF (12/30 Pages) Mitel Networks Corporation – Single Chip 2D Convolver with Integral Line Delays

PDSP16488A MA
In a multiple device system the load sequence will be
repeated for every device, and four additional address bits will
be generated on the CS3:0 pins. These address bits provide
the EPROM with a page address, with one page allocated to
each device in the system. Within each page only 73 locations
provide data for a convolver, the remainder are redundant as
in the single device system. The CS3:0 outputs must also be
decoded in order to provide individual chip enables for each
device. These can readily be derived by using an AS138 TTL
decoder. Bits in an internal control register determine the
number of times that the sequence is repeated.
If changes to the convolver operation are to be made
after power-on, activating the CE input on the MASTER or
SINGLE device will instigate the load procedure. Additional
EPROM address bits supplied from the system will allow
different filter coefficients to be used.
EPROM CONTROL LINES
X7:0
8 bit data from the EPROM to the MASTER or
SINGLE device. Otherwise data is received from
the previous device in the chain.
X14:8
Lower 7 address bits to the EPROM from a MAS-
TER or SINGLE device. Otherwise an input from
the data outs of the previous device.
X15
Tied to ground on a MASTER device to indicate the
EPROM mode.
R/W
Tied low on all devices.
DS
An output from a MASTER or SINGLE device
which provides a data strobe for the other devices.
CS3: 0
.
PC0
Four additional address bits for the EPROM which
are provided by the MASTER device. They allow
16 additional devices to be used and must be
externally decoded to provide chip enables.
An input on the MASTER device which is driven
from the PC1 output of the last device in the chain.
Used internally to terminate the write strobe. Con-
nected to previous PC1 outputs at intermediate
points in the chain. Not needed for a SINGLE
device.
PC1
An output connected to the PC0 input of the next
device in the chain. The last device feeds back to
the MASTER. Not needed for a SINGLE device.
CE
An enable which is produced by decoding CS3:0
from the MASTER. It is not needed for a MASTER
or SINGLE device which will always use the
bottom block of addresses with internally gener-
ated write strobes. It can however be used on
these devices to initiate a new load procedure
after the initial power on sequence.
PROG
An active low going signal produced by an
EPROM supported MASTER or SINGLE device.
An input to all other devices. It indicates that a
register load sequence is occuring, either after
power on, or as the result of CE as explained above.
It remains active until register 73 in the final device
has been loaded. Four bits in a control register
define the number of cascaded devices.
SYSTEM CONFIGURATION
The device is configured using a combination of the state of
the SINGLE and MASTER pins, and the contents of the four
Mode Control registers. In a MASTER or SINGLE device the
state of the X15 pin is used to define whether the system is
EPROM or host supported.
MODE CONTROL REGISTERS
REGISTER A Bit Allocation
BIT CODE
3:0 XXXX
6:4 000
6:4 001
6:4 010
6:4 011
6:4 101
7
0
7
1
FUNCTION
Number of extra devices from1-15
8 bit, 8x8 window, 10MHz max,
8x512 line delays.
16 bit, 8x4 window, 10MHz max,
4x512 line delays.
16 bit, 4x4 window, 20MHz max,
4x512 line delays.
8 bit, 8x4 window, 20MHz max,
4x1024 line delays.
8 bit, 4x4 window, 40MHz max,
4x1024 line delays
Multiplexed exp. data
Non-mux. exp. data
BITS 3:0 These bits are 'don't care' when using a host
computer but to a MASTER device, in an EPROM
supported system, they define the number of inter-
connected chips. The EPROM must contain con-
tiguous 128 byte blocks for each of the devices in
the system and a 4 bit counter in the MASTER
device will sequence through up to 16 block reads.
An internal comparator in the MASTER causes the
loading of the internal registers to cease when the
value in the counter equals that contained in these
bits. The bits are redundant in a SINGLE device
which only uses one 128 byte block.
BITS 6:4 These bits define one of the five basic configura-
tions. The line delays will automatically be config-
ured to match the chosen window size and pixel
accuracy. The maximum clock rate that is avail-
able to the user reflects the internal mutiplication
factor.
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