MT92220 Datasheet, PDF (28/210 Pages) Zarlink Semiconductor Inc – 1023 Channel Voice Over IP/AAL2 Processor

Data Sheet
MT92220
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
+0
Cell Header[31:0]
+4
Cell Payload
+8
Cell Payload
+C
Cell Payload
+10
Cell Payload
+14
Cell Payload
+18
Cell Payload
+1C
Cell Payload
+20
Cell Payload
+24
Cell Payload
+28
Cell Payload
+2C
Cell Payload
+30
Cell Payload
+34
Link to Next Free Cell [20:6]
+38
+3C
Figure 10 - Raw Cell Format (free cell)
Field
Link to Next Free Cell
Description
Points to the next free cell in SSRAM.
Table 10 - Fields and Description
There are multiple cell queues in the chip: 4 going to TX A, 2 going to TX B, 1 to the RX AAL2 and 1 to the RX CPU.
Each one of them keeps a list of cells pointed to in external memory. Each cell queue is of a programmable 2ⁿ size
between 64 cells (4 K bytes) and 8K cells (512 K bytes). If a cell queue overflows, a status bit will be flagged in
registers.
As is the case with packets, a cell handler module manages the read and write pointers to the queues. However,
instead of being contained in a small internal memory, all pointers and configuration of each cell queue is contained
in registers. However, a small internal memory is used to prefetch pointer to cells destined to each queue to prevent
starvation. The format of this memory is described in the following figure.
Zarlink Semiconductor Inc.
28