MT92220 Datasheet, PDF (1/210 Pages) Zarlink Semiconductor Inc – 1023 Channel Voice Over IP/AAL2 Processor

Features
• 1023 full-duplex PCM or ADPCM voice channels
over IP/UDP/RTP connections or over AAL2 VCs
• Simultaneously support of IP/UDP connection
and AAL2 VC
• RTP packaging optional in IP/UDP connection
• Supports IP version 4 and version 6
• Supports IP over Ethernet, ATM (AAL5) or POS
• Support Ethernet II, IEEE 802.3, LLC/SNAP and
PPP frames
• Supports Classical IP over ATM and LAN
Emulation (LANE) v1/v2
• Supports MPLS, MPOA and IEEE 802.1p/Q
ELAN-ID
• Packages voice in AAL2 according to I.363.2 and
I.366.2
• H.110 compliant TDM bus carrying PCM,
ADPCM or HDLC channels
• HDLC channels can be used to carry UDP
payload or AAL2 CPS-packet generated by
external agent
MT92220
1023 Channel Voice Over IP/AAL2
Processor
Data Sheet
December 2004
Ordering Information
MT92220
608 Pin EPBGA
-40°C to +85°C
• Support trunking in RTP and AAL2; up to 255
PCM/ADPCM channels per RTP connection or
AAL2 CID
• Support maximum 1500 bytes packet size
• Up to 4096 bytes of jitter buffer, absorbing +/- 256
ms of PDV
• Less than 250 usec of latency
• Injection of CPU-generated RTP or AAL2 CPS-
packets
• Reception of CPU-destinated RTP or AAL2 CPS-
packets
• Primary and secondary network interfaces
• Primary network interface supports 10/100 MII,
POS-PHY or Utopia level 1/2
M^MT^T9⁹0⁰4⁴1³
(8K to16.384M PLL)
optional
Intel/Motorola
CPU
Message Channel
HH.11010 Signals
Compatibility Clocks
and Frame
MT92220
H100/
H110
Interface
Clock
Recovery
uP
Interface
Service Timer
Second
Network
Interface
Primary
Network
Interface
Pad
SS
TDM
DataPath
SS/Padding
Calculator
RTP/AAL2
Assembly
RTP/AAL2
Disassembly
Packet
Identification
and Routing
Dual Memory Controler
Network
Memory
Controler
UTOPIA Port B
(PHY/SAR)
MII, POS, or
UTOPIA (PHY/SAR)
interface
SSRAM
(256k x18*)
SSRAM
(512k x18*)
SSRAM
SDRAM
(256k x36*) (4M x32*)
Memory Bank A Memory Bank B
Memory Bank C
*Typical RAM size for the support of 1023 channels. Parity bis are optionnal on all memories.
Figure 1 - MT92220 Block Diagram
1
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Copyright 2002-2004, Zarlink Semiconductor Inc. All Rights Reserved.