MT92220 Datasheet, PDF (132/210 Pages) Zarlink Semiconductor Inc – 1023 Channel Voice Over IP/AAL2 Processor

Data Sheet
MT92220
11.0 TX/RX TDM Data Paths
This chapter describes the data paths for all bytes transmitted and received with the H.110 interface.
11.1 TX TDM Data Path
The TX TDM section of the chip takes bytes from the H.110 interface and writes them into circular buffers in
SSRAM A. To do so, the MT92220 uses the TX Channel Association Memory to decide which of the 1023 time slots
on the H.110 bus it wants to treat. Each entry in the TX Channel Association Memory associates a time slot with
either a PCM buffer or an HDLC stream; the chip can support up to 1023 PCM buffers or up to 512 HDLC streams,
or any combination of the two (two PCM buffers cost the same as 1 HDLC stream). Any of the 1023 time slots
supported can also be configured as Low Latency Loopback: this means that the time slot will simply be looped
back onto another time slot on the H.110 bus.
This is the format of the TX Channel Association Memory:
80000h
80008h
Entry 0
Entry 1
81FF0h
81FF8h
Entry 1022
Entry 1023
TX Channel Association Memory Entry
b 15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
+0
+2
Stream/Buffer Tag
+4 AS
TSST [11:0]
+6
Link to Next Entry
Figure 72 - TX Channel Association Memory
Zarlink Semiconductor Inc.
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