MUN5311DW Datasheet, PDF (1/29 Pages) Weitron Technology – Dual Bias Resistor Transistor NPN+PNP Silicon

DATA SHEET
SEMICONDUCTOR
MUN5311DW Series
Dual Bias Resistor Transistors
NPN and PNP Silicon Surface Mount
H
Transistors with Monolithic Bias
Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network
consisting of two resistors; a series base resistor and a base–emitter resistor. These digital tran-
sistors are designed to replace a single device and its external resistor bias network. The BRT
eliminates these individual components by integrating them into a single device. In the
MUN5311DW series, two complementary BRT devices are housed in the SOT–363 package
which is ideal for low power surface mount applications where board space is at a premium.
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• We declare that the material of product compliance with RoHS requirements.
6
5
4
1
2
3
SOT-363/SC-88
MAXIMUM RATINGS (T A = 25°C unless otherwise noted, common for Q 1
and Q 2 , – minus sign for Q 1 (PNP) omitted)
Rating
Symbol Value Unit
Collector-Base Voltage
V CBO
50
Vdc
Collector-Emitter Voltage
V CEO
50
Vdc
Collector Current
Emitter-Base Voltage
IC
V EBO
100 mAdc
6 Vdc
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Symbol
Max
Unit
Total Device Dissipation
PD
187 (Note 1.) mW
T A = 25°C
256 (Note 2.)
Derate above 25°C
1.5 (Note 1.) mW/°C
2.0 (Note 2.)
Thermal Resistance –
R θJA
670 (Note 1.)
°C/W
Junction-to-Ambient
490 (Note 2.)
Characteristic
(Both Junctions Heated)
Symbol
Max
Total Device Dissipation
T A = 25°C
Derate above 25°C
Thermal Resistance –
Junction-to-Ambient
Thermal Resistance –
Junction-to-Lead
P_D
R θJA
R θJL
250 (Note 1.)
385 (Note 2.)
2.0 (Note 1.)
3.0 (Note 2.)
493 (Note 1.)
325 (Note 2.)
188 (Note 1.)
208 (Note 2.)
Junction and Storage
Temperature
T J , T stg
–55 to +150
1. FR–4 @ Minimum Pad
http://www.yeashin.com
2. FR–4 @ 1.0 x 1.0 inch Pad
1
Unit
mW
mW/°C
°C/W
°C/W
°C
6
5
4
Q₂
R1 _R2
R2
Q₁
R1
1
2
3
MARKING DIAGRAM
6
5
4
XX
1
2
3
xx = Device Marking
= (See Page 2)
DEVICE MARKING
INFORMATION
See specific marking information in
the device marking table on page 2 of
this data sheet.
REV.02 20130927