YMF781 Datasheet, PDF (9/14 Pages) YAMAHA CORPORATION – APL-1 Automobile sound PLayer-1

YMF781
T_XR
T_XF
T_XH
T_XL
XI
T_XFREQ
V_IH= 0.75*VDD
V_IL= 0.25*VDD
T_R
Input Signals
except XI
T_F
V_IH= 0.75*VDD or 0.75*VDDC
V_IL= 0.25*VDD or 025*VDDC
・Clock Sync Serial Interface
Ｉtem
Symbol ï¼­in. ï¼´yp. ï¼­ax. ï¼µnit
SCLKN frequency (Serial transfer speed)
1 / T_SFREQ
1
2
MHz
SCLKN High time
T_SH
220
ns
SCLKN Low time
T_SL
220
ns
SDI set-up time
T_SIS
0
ns
SDI hold time
T_SIH
75
ns
SDO output delay time
T_SOD
200
ns
SDO output hold time (*1)
T_SOH
110
ns
SRDYN output delay time (L→H) (*2)
T_SRDD
300
ns
Conditions: T_OP= -40 to 85℃, VDD= 3.0 to 3.6V, VDDC= 3.0 to 3.6V or 4.75 to 5.25V, Capacitor load=50pF
(*1) The last SDO output data is held until the next SCLKN falling edge is detected.
(*2) Time to the High level in synchronization with SCLKN, when the first 1 bit is transmitted or received.
The falling timing depends on the transmit/receive process of the internal Control CPU.
SCLKN
SDI
SDO
SRDYN
T_SFREQ
T_SL
T_SH
T_SIS
T_SIH
T_SOD
T_SOH
T_SRDD
V_IH= 0.75*VDDC
V_IL= 0.25*VDDC
9