YMF781 Datasheet, PDF (10/14 Pages) YAMAHA CORPORATION – APL-1 Automobile sound PLayer-1

YMF781
・Asynchronous Serial Interface （UART）
Ｉtem
Symbol ï¼­in. ï¼´yp. ï¼­ax. ï¼µnit
Transfer Frequency (Baud rate: fixed to x16) 1 / T_RXD
9
RXD allowable frequency error (*1)
-2
144
kHz
+2
%
Conditions: T_OP= -40 to 85℃, VDD= 3.0 to 3.6V, VDDC= 3.0 to 3.6V or 4.75 to 5.25V, Capacitor load=50pF
(*1) In the case of 10 bits including the start bit and the stop bit.
・External Memory Interface
Ｉtem
Symbol ï¼­in. ï¼´yp. ï¼­ax. ï¼µnit
Data (D) Set-up time
T_DS
10
ns
Data (D) Hold time
T_DH
10
ns
Address (A) Output Delay time
T_AD
40
ns
Control Signal Output Delay time (*1)
T_CTLD
40
ns
Data (D) Output Delay time
T_DD
80
ns
Data (D) Output turn-on time
T_DT
20
ns
Conditions: T_OP= -40 to 85℃, VDD= 3.0 to 3.6V, VDDC= 3.0 to 3.6V or 4.75 to 5.25V, Capacitor load=50pF
(*1) LBN/LWRN, UBN/UWRN, WRN, RDN, and CS*N
Internal Master Clock
MCK
A[21:0]
D[15:00]
(Output)
D[15:00]
(Input)
LWRN, UWRN,
WRN（3clock or less）
LWRN, UWRN,
WRN（4clock or more）
LBN, UBN,
CS*N, RDN
T_AD
T_DD
T_DT
T_CTLD
T_CTLD
T_CTLD
T_AD
T_DD
T_DS
T_DH
T_CTLD
T_CTLD
T_CTLD
Access time 2 to 9 clocks (variable)
※Note that the output timing of LWRN, UWRN, and WRN differs in the access time of 3 clocks or less and that of 4 clocks or more.
10