YMF781 Datasheet, PDF (6/14 Pages) YAMAHA CORPORATION – APL-1 Automobile sound PLayer-1

■Block Diagram
YMF781
APL-1 Control Interface
External Memory Interface
RSTN
XI
XO
Control CPU
Synthesizer
Core
（MA-5）
Power-down
Controller
Boot ROM
Work RAM
Timer
WDT
Others
+
EQ3
EQ2
EQ1
SPOUT1
SPOUT2
SPVDD
SPVSS
AOR
AOL
■Overview of the block
The overview function of each block and the flow of a signal are explained.
Control CPU
The Control CPU controls APL-1 in all as well as the Synthesizer Core controls such as a sequencer function.
Synthesizer Core
Hybrid Synthesizer Core equivalent to MA-5, which is a synthesizer LSI for mobile phone.
The synthesizer performs play of the sound contents, LED controls, etc.
External Memory Interface
The interface connects APL-1 to the external memory.
Accessible memory space is up to 8MByte. (CS0N:４ＭByte＋CS1N:２ＭByte＋CS2N:２ＭByte.)
SRAM with the specification of byte access is necessary.
From P30-P37 can be used as the output port when only one external ROM is used.
APL-1 Control Interface
APL-1 is controlled through the APL-1 Control Interface.
Mode 1 and Mode 2 can be selected according to the settings of SEL terminal.
In Mode １, Clock Sync Serial and Asynchronous Serial (UART) can be switched and used by the HSEL terminal.
In Mode 2, Asynchronous Serial (UART) and command port (A mode, which identify command by the change of
data that inputted into P20-P26) can be used at the same time.
P01 and P11 can be used as input port, and P00 and P10 can be used as output port, depending on the settings.
Timing Generator
Clocks used in the APL-1 are generated.
Power-down Controller
The controller controls APL-1 in the power-saving mode.
Boot ROM, Work RAM, Timer, WDT, etc.
The peripheral devices of the Control CPU in the APL-1.
6