YMF754 Datasheet, PDF (54/60 Pages) YAMAHA CORPORATION – DS-1E

YMF754
4-3. PCI Interface (Fig.3, 4)
Item
Symbol
Condition
Min. Typ. Max.
PCICLK Cycle Time
PCICLK High Time
PCICLK Low Time
PCICLK Slew Rate
t_PCYC
t_PHIGH
t_PLOW
-
30
-
-
11
-
-
11
-
-
1
-
4
PCICLK to Signal Valid Delay
t_PVAL (Bused signal)
t_PVAL(PTP) (Point to Point)
2
-
11
2
-
12
Float to Active Delay
t_PON
2
-
-
Active to Float Delay
t_POFF
-
-
28
t_PSU (Bused signal)
7
-
-
Input Setup Time to PCICLK
*11 (Point to Point) 10
-
-
t_{PSU(PTP) *12 (Point to Point)}
12
-
-
Input Hold Time for PCICLK
t_PH
0
-
-
Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=2.5±0.2 V, LVDD=2.5±0.2 V, C_L=10 pF
*11: This characteristic is applicable to REQ# and PCREQ# signal.
*12: This characteristic is applicable to GNT# and PCGNT# signal.
Unit
ns
ns
ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
PCICLK
0.5 VDD3
0.4 VDD3
0.3 VDD3
t _PHIGH
t _PLOW
t _PCYC
Fig.3: PCI Clock timing
PCICLK
OUTPUT
Tri-State
OUTPUT
t _PVAL
t _PON
t _POFF
INPUT
1.5 V
1.5 V
t _PSU
t _PH
1.5 V
Fig.4: PCI Bus Signals timing
June 28, 1999
-54-