YMF754 Datasheet, PDF (53/60 Pages) YAMAHA CORPORATION – DS-1E

YMF754
4. AC Characteristics
4-1. Master Clock (Fig.1)
Item
Symbol Min. Typ. Max. Unit
XI24 Cycle Time
t_XICYC
-
40.69
-
ns
XI24 High Time
t_XIHIGH
13
-
24
ns
XI24 Low Time
t_XILOW
13
-
24
ns
Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=2.5±0.2 V, LVDD=2.5±0.2 V
XI24
2.3 V
1.65 V
1.0 V
t _XIHIGH
t _XILOW
t _XICYC
Fig.1: XI24 Master Clock timing
4-2. Reset (Fig.2)
Item
Symbol Min. Typ. Max. Unit
Reset Active Time after Power Stable
t_RST
1
-
Power Stable to Reset Rising Edge
t_RSTOFF
10
-
Reset Slew Rate
-
50
-
-
ms
-
ms
- mV/ns
Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=2.5±0.2 V, LVDD=2.5±0.2 V, C_L=50 pF
3.0 V
PVDD, VDD
CVDD, LVDD
RST#
2.3 V
t _RSTOFF
t _RST
0.8 V
Fig.2: PCI Reset timing
June 28, 1999
-53-