YMF754 Datasheet, PDF (23/60 Pages) YAMAHA CORPORATION – DS-1E

YMF754
b9................PR1: AC’97 Power Down Control 1
This bit controls the power state of the DAC in the Primary AC’97.
“0”: Normal
(default)
“1”: Power down
b10..............PR2: AC’97 Power Down Control 2
This bit controls the power state of the Analog Mixer (Vref still on) in the Primary AC’97. This power
state retains the Reference Voltage of the AC’97.
“0”: Normal
(default)
“1”: Power down
b11..............PR3: AC’97 Power Down Control 3
This bit controls the power state of the Analog Mixer (Vref off) in the Primary AC’97. This power
state removes Reference Voltage of the AC’97.
“0”: Normal
(default)
“1”: Power down
b12..............PR4: AC’97 Power Down Control 4
This bit controls the power state of the AC-link in the Primary AC’97.
“0”: Normal
(default)
“1”: Power down
b13..............PR5: AC’97 Power Down Control 5
Setting this bit to “1” disables the internal clock of the Primary AC’97. In case the AC’97 is used with
DS-1E, the master clock is supplied from DS-1E. Therefore, when the clock is stopped completely, set
PR5 bits to “1” firstly, then the CMCD bit should be set to “1” after duration of 1ms or longer.
“0”: Normal
(default)
“1”: Disable
b14..............PR6: AC’97 Power Down Control 6
This bit controls PR6 bit status of the power control register in the Primary AC’97.
b15..............PR7: AC’97 Power Down Control 7
This bit controls PR7 bit status of the power control register in the Primary AC’97.
Respective data set to b[15:8] are correspondingly set into the “Power down Ctrl/Stat” register in the Primary
AC’97 via the AC-Link. These are not set into the “Power down Ctrl/Stat” register in the Secondary AC’97.
June 28, 1999
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