YMF724F Datasheet, PDF (47/50 Pages) YAMAHA CORPORATION – high performance audio controller for the PCI Bus

YMF724F
CBCLK
SYNC
CSDO
t _CBICYC
2.2 V
1.5 V
t _CBIHIGH
t _CBILOW
t _CVAL
t _CSYHIGH
t _CVAL
t _COH
2.2 V
0.8 V
0.8 V
t _COH
t _CSYLOW
2.2 V
t _CSYCYC
1.5 V
0.8 V
CSDI
t _CISU
t _CIH
2.2 V
0.8 V
Fig.6: AC-link timing
4-6 AC3F2 Interface (Fig.7, 8)
Item
Symbol
Condition
Min. Typ. Max. Unit
ASCLK Cycle Time
t_ASCCYC
-
325
-
ns
ASCLK High Time
t_ASCHIGH
140
-
180
ns
ASCLK Low Time
t_ASCLOW
140
-
180
ns
ASCLK to Signal Valid Delay t_ACVAL *14
-
-
50
ns
Output Hold Time for ASCLK t_ACOH *14
-10
-
-
ns
Input Setup Time to ASCLK
t_ACISU *15
20
-
-
ns
Input Hold Time for ASCLK
t_ACIH *15
10
-
-
ns
ABCLK Cycle Time
t_ABICYC
-
325
-
ns
ABCLK High Time
t_ABIHIGH
140
-
180
ns
ABCLK Low Time
t_ABILOW
140
-
180
ns
ABCLK to Signal Valid Delay t_ASVAL *16
-
-
50
ns
Output Hold Time for ABCLK t_ASOH *16
-10
-
-
ns
Input Setup Time to ABCLK
t_ASISU *17
20
-
-
ns
Input Hold Time for ABCLK
t_ASIH *17
10
-
-
ns
Note) Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, C_L=50 pF
*14: This characteristic is applicable to ACS and ACDO signal.
*15:This characteristic is applicable to ACDI signal.
*16: This characteristic is applicable to ASDO and ALRCK signal.
*17: This characteristic is applicable to ASDI signal.
January 14, 1999
-47-