YMF724F Datasheet, PDF (46/50 Pages) YAMAHA CORPORATION – high performance audio controller for the PCI Bus

YMF724F
4-4. AC’97 / AC3F2 Master Clock (Fig.5)
Item
Symbol Min. Typ. Max. Unit
CMCLK Cycle Time
t_CMCYC
-
40.69
-
ns
CMCLK High Time
t_CMHIGH
8
-
-
ns
CMCLK Low Time
t_CMLOW
8
-
ns
CMCLK Rising Time
t_CMR
-
4.6
-
ns
CMCLK Falling Time
t_CMF
-
2.1
-
ns
Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, C_L=50 pF
t _CMR
CMCLK
t _CMF
3.5 V
2.5 V
0.4 V
t _CMHIGH
t _CMLOW
t _CMCYC
Fig.5: Master Clock timing for AC’97 and AC3F2
4-5. AC-link (Fig.6)
Item
Symbol
Condition
Min. Typ. Max. Unit
CBCLK Cycle Time
CBCLK High Time
CBCLK Low Time
CSYNC Cycle Time
CSYNC High Time
CSYNC Low Time
CBCLK to Signal Valid Delay
Output Hold Time for CBCLK
Input Setup Time to CBCLK
Input Hold Time for CBCLK
Warm Reset Width
t_CBICYC
t_CBIHIGH
t_CBILOW
t_CSYCYC
t_CSYHIGH
t_CSYLOW
t_CVAL *12
t_COH *12
t_CISU *13
t_CIH *13
-
81.4
-
ns
35
40.7
45
ns
35
40.7
45
ns
-
20.8
-
ns
-
1.3
-
ns
-
19.5
-
ns
-
-
20
ns
0
-
-
ns
15
-
-
ns
5
-
-
ns
-
1.3
-
µs
Note) Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, C_L=50 pF
*12: This characteristic is applicable to CSYNC and CSDO signal.
*13: This characteristic is applicable to CSDI signal.
January 14, 1999
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