YMF724F Datasheet, PDF (23/50 Pages) YAMAHA CORPORATION – high performance audio controller for the PCI Bus

YMF724F
b12..............PR4: AC’97 Power down Control 4
This bit controls the power state of the AC-link in AC’97.
“0”: Normal
(default)
“1”: Power down
b13..............PR5: AC’97 Power down Control 5
Setting this bit to “1” disables the internal clock of AC’97. In case AC’97 is used with DS-1, the master
clock is supplied from DS-1. Therefore, when the clock of AC’97 is stopped completely, set both PR5
and PSN bits to “1”.
“0”: Normal
(default)
“1”: Disable
b[15:14] ......AC’97 Power down Control 6 and 7
These bits control PR6 and PR7 status of the power control register in AC’97.
Master
(24.576MHz)
DMC
PLL0
33.87MHz
DPLL0
PLL1
49.152MHz
DPLL1
PSL0
Legacy func. 0
FM Synthesizer
SB Pro
PSL1
Legacy func. 1
MPU401
Joystick
PSN
PCI func. 0
AC3F2 I/F
AC'97 I/F
H/W Vol.
PCI Audio
SRC
SPDIF
PCICLK
(33MHz)
PCI func. 1
PCI I/F
PC/PCI
D-DMA
S-IRQ
- Set DPLL0, DPLL1, PSL0, PSL1 and PSN bits to “1”, when DMC bit is set to “1”.
- Set PSL0 and PSL1 bits to “1”, when DPLL0 bit is set to “1”.
- Set PSN bit to “1”, when DPLL1 bit is set to “1”.
January 14, 1999
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