XA2C128 Datasheet, PDF (8/16 Pages) Xilinx, Inc – AEC-Q100 device qualification and full PPAP support

XA2C128 CoolRunner-II Automotive CPLD
R
Internal Timing Parameters (Continued)
Symbol
Parameter⁽¹⁾
I/O Standard Time Adder Delays 2.5V CMOS
T_IN25
Standard input adder
T_HYS25
Hysteresis input adder
T_OUT25
Output adder
T_SLEW25
Output slew rate adder
I/O Standard Time Adder Delays 3.3V CMOS/TTL
T_IN33
Standard input adder
T_HYS33
Hysteresis input adder
T_OUT33
Output adder
T_SLEW33
Output slew rate adder
Notes:
1. 1.5 ns input pin signal rise/fall.
-7
Min.
Max.
-
0.7
-
3.0
-
0.9
-
4.0
-
0.6
-
3.0
-
1.4
-
4.0
-8
Min.
Max.
-
0.7
-
3.0
-
0.9
-
4.0
-
0.6
-
3.0
-
1.4
-
4.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics
VCC = VCCIO = 1.8V, 25^oC
5.0
4.8
4.6
Switching Test Conditions
VCC
Device
Under Test
R1
R2
CL
Test Point
4.4
4.2
4.0
1
2
4
8
16
Number of Outputs Switching
DS093_02_050103
Figure 2: Derating Curve for T_PD
Output Type
LVTTL33
R1
268Ω
R2
235Ω
LVCMOS33
275Ω
275Ω
LVCMOS25
188Ω
188Ω
LVCMOS18
112.5Ω 112.5Ω
LVCMOS15
150Ω
150Ω
Notes:
1. CL includes test fixtures and probe capacitance.
2. 1.5 nsec maximum rise/fall times on inputs.
Figure 3: AC Load Circuits
CL
35 pF
35 pF
35 pF
35 pF
35 pF
DS092_03_092302
8
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DS554 (v1.1) May 5, 2007
Product Specification