XA2C128 Datasheet, PDF (11/16 Pages) Xilinx, Inc – AEC-Q100 device qualification and full PPAP support

R
XA2C128 CoolRunner-II Automotive CPLD
Pin Descriptions (Continued)
Function
Block
Macro-
cell
VQG100 CPG132 I/O Bank
7
1
77
C12
2
7
2
78
B12
2
7
3
-
A12
2
7
4
79
C11
2
7
5
80
B11
2
7
6
81
A11
2
7
7
-
C10
2
7
8
-
-
-
7
9
-
-
-
7
10
-
-
-
7
11
82
A10
2
7
12
-
C9
2
7
13
85
A8
2
7
14
86
B8
2
7
15
87
C8
2
7
16
89
B7
2
Pin Descriptions (Continued)
Function
Block
Macro-
cell
VQG100 CPG132 I/O Bank
8
1
-
N14
1
8
2
53
N13
1
8
3
52
P14
1
8
4
50
P12
1
8
5
-
M11
1
8
6
49
N11
1
8
7
-
-
-
8
8
-
-
-
8
9
-
-
-
8
10
-
-
-
8
11
-
P11
1
8
12
46
P10
1
8
13
44
P9
1
8
14
43
M8
1
8
15
42
N8
1
8
16
41
P8
1
Notes:
1. GTS = global output enable, GSR = global reset/set, GCK =
global clock, CDRST = clock divide reset, DGE = DataGATE
enable.
2. GCK, GSR, and GTS pins can also be used for general
purpose I/O.
DS554 (v1.1) May 5, 2007
www.xilinx.com
11
Product Specification