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XA2C128 Datasheet, PDF (6/16 Pages) Xilinx, Inc – AEC-Q100 device qualification and full PPAP support
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XA2C128 CoolRunner-II Automotive CPLD
R
-7
-8
Symbol
Parameter
Min. Max. Min. Max. Units
TSU1
Setup time fast (single p-term)
3.0
- 3.0 -
ns
TSU2
Setup time (OR array)
3.5
- 3.5 -
ns
THD
Direct input register hold time
0.0
-
0.0
-
ns
TH
Hold time (Or array or p-term)
0.0
-
0.0
-
ns
TCO
FTOGGLE(1)
FSYSTEM1(2)
FSYSTEM2(2)
FEXT1(3)
FEXT2(3)
Clock to output
Internal toggle rate
Maximum system frequency
Maximum system frequency
Maximum external frequency
Maximum external frequency
-
5.4
-
5.4 ns
- 300 - 300 MHz
- 152 - 152 MHz
- 141 - 141 MHz
- 119 - 119 MHz
- 112 - 112 MHz
TPSUD
Direct input register p-term clock setup time
3.1
-
3.1
-
ns
TPSU1
P-term clock setup time (single p-term)
1.5
-
1.5
-
ns
TPSU2
P-term clock setup time (OR array)
2.0
-
2.0
-
ns
TPHD
Direct input register p-term clock hold time
0.2
- 0.2 -
ns
TPH
P-term clock hold
1.0
-
1.0
-
ns
TPCO
P-term clock to output
-
7.3
-
7.3 ns
TOE/TOD
Global OE to output enable/disable
-
7.5
-
7.5 ns
TPOE/TPOD
P-term OE to output enable/disable
-
8.5
-
8.5 ns
TMOE/TMOD Macrocell driven OE to output enable/disable
-
9.9
-
9.9 ns
TPAO
P-term set/reset to output valid
-
8.1
-
8.1 ns
TAO
Global set/reset to output valid
-
7.6
-
7.6 ns
TSUEC
Register clock enable setup time
3.5
-
3.5
-
ns
THEC
Register clock enable hold time
0.0
-
0.0
-
ns
TCW
Global clock pulse width High or Low
1.6
-
1.6
-
ns
TAPRPW
Asynchronous preset/reset pulse width (High or Low)
7.5
-
7.5
-
ns
TPCW
P-term pulse width High or Low
7.5
-
7.5
-
ns
TDGSU
Set-up before DataGATE latch assertion
0.0
-
0.0
-
ns
TDGH
Hold to DataGATE latch assertion
6.0
-
6.0
-
ns
TDGR
DataGATE recovery to new data
-
9.0
9.0 ns
TDGW
DataGATE low pulse width
4.0
-
4.0
-
ns
TCDRSU
CDRST setup time before falling edge GCLK2
2.0
-
2.0
-
ns
TCDRH
TCONFIG(4)
Hold time CDRST after falling edge GCLK2
Configuration time
0.0
- 0.0 -
ns
- 350 - 350 us
Notes:
1. FTOGGLE is the maximum clock frequency to which a T flip-flop can reliably toggle (see the CoolRunner-II Automotive CPLD family
data sheet).
2. FSYSTEM1 is the internal operating frequency for a device with 16-bit resetable binary counter through one p-term per macrocell
while FSYSTEM2 is through the OR array (one counter per function block).
3. FEXT1 (1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array.
4. Typical configuration current during TCONFIG is 10 mA.
6
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DS554 (v1.1) May 5, 2007
Product Specification
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