XQ4000XL Datasheet, PDF (7/22 Pages) Xilinx, Inc – Ceramic and plastic packages

R
QPRO XQ4000XL Series QML High-Reliability FPGAs
CLB Switching Characteristics (Continued)
Symbol
Description
Hold Time After Clock K
T_CKI
T_CKIH
T_CKHH0
T_CKHH1
T_CKHH2
T_CKDI
T_CKEC
T_CKR
Clock
F/G inputs
F/G inputs via H
C inputs via SR/H0 through H
C inputs via H1 through H
C inputs via D_IN/H2 through H
C inputs via D_IN/H2
C inputs via EC
C inputs via SR, going Low (inactive)
T_CH
Clock High time
T_CL
Clock Low time
Set/Reset Direct
T_RPW Width (High)
T_RIO
Delay from C inputs via S/R, going High to Q
Global Set/Reset
T_MRW Minimum GSR pulse width
T_MRQ Delay from GSR input to any Q
F_TOG Toggle frequency (MHz) (for export control)
-3
Min
Max
-1
Min
Max
Units
0
-
0
-
ns
0
-
0
-
ns
0
-
0
-
ns
0
-
0
-
ns
0
-
0
-
ns
0
-
0
-
ns
0
-
0
-
ns
0
-
0
-
ns
3.0
-
2.5
-
ns
3.0
-
2.5
-
ns
3.0
-
2.5
-
ns
-
3.7
-
2.8
ns
-
19.8
-
15.0
See page 17 for T_RRI values per device.
-
166
-
200
ns
MHz
DS029 (v1.3) June 25, 2000
www.xilinx.com
7
Product Specification
1-800-255-7778