XQ4000XL Datasheet, PDF (15/22 Pages) Xilinx, Inc – Ceramic and plastic packages

R
QPRO XQ4000XL Series QML High-Reliability FPGAs
Global Early Clock BUFEs 3, 4, 7, and 8 Setup and Hold for IFF and FCL^(1,2)
-3
-1
Symbol
Description
Device
Min
Min
No Delay
T_PSEN/T_PHEN
T_PFSEN/T_PFHEN
Global early clock and IFF⁽³⁾
Global early clock and FCL⁽⁴⁾
XQ4013XL
1.2 / 4.7
-
XQ4036XL
1.2 / 6.7
-
XQ4062XL
1.2 / 8.4
-
XQ4085XL
-
0.9 / 6.6
Partial Delay
T_PSEPN/T_PHEP
T_PFSEP/T_PFHEP
Global early clock and IFF⁽³⁾
Global early clock and FCL⁽⁴⁾
XQ4013XL
5.4 / 0.0
-
XQ4036XL
6.4 / 0.8
-
XQ4062XL
8.4 / 1.5
-
XQ4085XL
-
11.0 / 0.0
Full Delay
T_PSEPD/T_PHED
Global early clock and IFF⁽³⁾
XQ4013XL
10.0 / 0.0
-
XQ4036XL
12.2 / 0.0
-
XQ4062XL
13.1 / 0.0
-
XQ4085XL
-
13.6 / 0.0
Notes:
1. The XQ4013XL, XQ4036XL, and XQ4062XL have significantly faster partial and full delay setup times than other devices.
2. Input setup time is measured with the fastest route and the lightest load. Input hold time is measured using the furthest distance and
a reference load of one clock pin per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock
loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin
no-delay input hold specification.
3. IFF = Input Flip-Flop or Latch
4. FCL = Fast Capture Latch
DS029 (v1.3) June 25, 2000
www.xilinx.com
15
Product Specification
1-800-255-7778