XQ4000XL Datasheet, PDF (12/22 Pages) Xilinx, Inc – Ceramic and plastic packages

QPRO XQ4000XL Series QML High-Reliability FPGAs
R
Output Flip-Flop, Clock to Out, BUFGEs 3, 4, 7, and 8
Symbol
T_ICKEOF
Description
Global early clock to output using OFF
Values are for BUFGEs 3, 4, 7, and 8.
All
Device
Min
XQ4013XL
1.8
XQ4036XL
1.8
XQ4062XL
2.0
XQ4085XL
2.2
-3
-1
Max
Max Units
8.8
-
ns
9.7
-
ns
10.9
-
ns
-
9.3
ns
Notes:
1. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using
the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For
designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can
be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode
configurations.
2. Output timing is measured at ~50% V_CC threshold with 50 pF external capacitive load.
Capacitive Load Factor
Figure 1 shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the specified
3
output delay if the load capacitance is different than 50 pF.
For example, if the actual load capacitance is 120 pF, add
2
2.5 ns to the specified delay. If the load capacitance is
20 pF, subtract 0.8 ns from the specified output delay.
1
Figure 1 is usable over the specified operating conditions of
voltage and temperature and is independent of the output
slew rate control.
0
-1
-2
0
20 40 60 80 100 120 140
Capacitance (pF)
DS029_03_011300
Figure 1: Delay Factor at Various Capacitive Loads
12
www.xilinx.com
DS029 (v1.3) June 25, 2000
1-800-255-7778
Product Specification