XC4036XLA Datasheet, PDF (7/14 Pages) Xilinx, Inc – XC4000XLA/XV Field Programmable Gate Arrays

R
XC4000XLA/XV Field Programmable Gate Arrays
I/O Signalling Standards
XLA and XV devices are compatible with TTL, LVTTL, PCI
3V, PCI 5V and LVCMOS signalling. The various standards
are illustrated in Table 6 and the signaling environment is
illustrated in Figure 4.
VCC Clamping
XLA/XV devices are fully 5V TTL I/O compatible if VCC
clamping is not enabled. The I/O pins can withstand input
voltages up to 7V. With VCC clamping enabled, the XLA/XV
devices will begin to clamp input voltages to one diode volt-
age drop above VCC. In both cases negative voltage is
clamped to one diode voltage drop below ground.
XLA/XV devices maintain LVTTL I/O compatibility when
VCC clamping is enabled, however full 5.0V TTL I/O com-
patibility is sacrificed.
Overshoot and Undershoot
Ringing wave forms are allowed on XLA/XV inputs as long
as undershoot is limited to -2.0V and overshoot is limited to
+7.0V and current is limited to 100 mA for less than 10 ns.
If VCC clamping is enabled then overshoot will begin to be
clamped at VCC/VCCIO plus one diode voltage drop and
undershoot will be clamped to ground minus one diode volt-
age drop. In either case the current must be limited to 100
mA per pin for less than 10 ns.
Table 6: I/O Standards supported by XC4000XLA and XV FPGAs
Signaling
Standard
VCC
Clamping Output Drive
V_{IH_MAX}
V_{IH MIN}
V_{IL MAX}
V_{OH MIN}
V_{OL MAX}
TTL
Not allowed 12/24 mA
5.5
2.0
0.8
2.4
0.4
LVTTL
OK
12/24 mA
3.6
2.0
0.8
2.4
0.4
PCI5V
Not allowed
24 mA
5.5
2.0
0.8
2.4
0.4
PCI3V
Required
LVCMOS 3V
OK
12 mA
12/24 mA
3.6
50% of
30% of
90% of
10% of
VCC/VCCIO VCC/VCCIO VCC/VCCIO VCC/VCCIO
6
3.6
50% of
30% of
90% of
10% of
VCC/VCCIO VCC/VCCIO VCC/VCCIO VCC/VCCIO
5.0 V Power
3.3 V Power
2.5 V Power
V_CC (5 V)
5 Volt Device
TTL
LVTTL
V_CCIO V_CCINT
XC4000XV
LVTTL
V_CC (3.3 V)
3.3 Volt Device
Ground
X7147
Figure 4: The Signalling Environment for XLA/XV FPGAS. For XLA devices the VCCIO and VCCINT supplies are
replaced by a single 3.3 Volt VCC supply, however, all indicated I/O signalling is still supported.
Express Configuration Mode
Express configuration mode is similar to Slave Serial con-
figuration mode, except that data is processed one byte per
CCLK cycle instead of one bit per CCLK cycle. An external
source is used to drive CCLK, while byte-wide data is
loaded directly into the configuration data shift registers
(Figure 5). A CCLK frequency of 10 MHz is equivalent to a
80 MHz serial rate, because eight bits of configuration data
are loaded per CCLK cycle. Express mode does not sup-
port CRC error checking, but does support constant-field
error checking. A length count is not used in Express mode.
Express mode must be specified as an option to the BitGen
program, which generates the bitstream. The Express
mode bitstream is not compatible with the other configura-
tion modes. Express mode is selected by a <010> on the
mode pins (M2, M1, M0).
The first byte of parallel configuration data must be avail-
able at the D inputs of the FPGA a short setup time before
the second rising CCLK edge. Subsequent data bytes are
DS015 (v1.3) October 18, 1999 - Product Specification
6-163