XC4036XLA Datasheet, PDF (3/14 Pages) Xilinx, Inc – XC4000XLA/XV Field Programmable Gate Arrays

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XC4000XLA/XV Field Programmable Gate Arrays
Three-State Register
Table 2: K-Factor and Relative Power.
XC4000XLA/XV devices incorporate an optional register
controlling the three-state enable in the IOBs.The use of
the three-state control register can significantly improve
output enable and disable time.
FastCLK Clock Buffers
The XLA/XV devices incorporate FastCLK clock buffers.
Two FastCLK buffers are available on each of the right and
left edges of the die. Each FastCLK buffer can provide a
fast clock signal (typically < 1.5 ns clock delay) to all the
IOBs within the IOB octant containing the buffer. The Fast-
CLK buffers can be instantiated by use of the BUFFCLK
symbols. (In addition to FastCLK buffers, the Global Early
BUFGE clock buffers #1, #2, #5, and #6 can also provide
fast clock signals (typically < 1.5 ns clock delay) to IOBs on
the top and bottom of the die.
FPGA Family
XC4000XL
XC4000XLA
XC4000XV
K-Factor
28
17
13
Power
Power
Relative To Relative To
XL
XLA
1.00
1.65
0.60
1.00
0.35
0.58
XLA/XV Logic Performance
XC4000XLA/XV devices feature 30% faster device speed
than XL devices, and consistent performance is achieved
across all family members. Table 3 illustrates the perfor-
mance of the XLA devices. For details regarding the imple-
mentation of these benchmarks refer to XBRF15 “Speed
Metrics for High Performance FPGAs”.
Table 3: XLA/XV Estimated Benchmark Performance
XLA/XV Power Requirements
Register - Register
Benchmarks
Size
Maximum
Frequency
XC4000XLA devices require 40% less power per CLB than
8-Bit
172 MHz
equivalent XL devices. XC4000XV devices require 42%
Adder
16-Bit
144 MHz
less power per CLB than equivalent XLA devices and 65%
less power than XL devices The representative K-Factor for
32-Bit
108 MHz
6
the following families can be found in Table 2. The K-Factor
2 Cascaded Adders
16-Bit
94 MHz
predicts device current for typical user designs and is
4 Cascaded Adders
16-Bit
57 MHz
based on filling the FPGA with active 16-Bit counters and
1 Level
314 MHz
measuring the device current at 1 MHz. This technique is
described in XBRF14 “A Simple Method of Estimating
Power in XC4000XL/EX/E FPGAs”. To predict device
power (P) using the K-Factor use the following formula:
Cascaded 4LUTs
2 Level
4 Level
6 Level
1 CLBs
193 MHz
108 MHz
75 MHz
325 MHz
P=V*K*N*F; where:
P= Device Power
V= Power supply voltage
K= the Device K-Factor
N = number of active registers
F = Frequency in MHz
Interconnect
(Manhattan Distance)
Dual Port RAM
(Pipelined)
4 CLBs
16 CLBs
64 CLBs
128 CLBs
8-Bits by 16
8-Bits by 256
260 MHz
185 MHz
108 MHz
81 MHz
172 MHz
172 MHz
DS015 (v1.3) October 18, 1999 - Product Specification
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