XC4036XLA Datasheet, PDF (10/14 Pages) Xilinx, Inc – XC4000XLA/XV Field Programmable Gate Arrays

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XC4000XLA/XV Field Programmable Gate Arrays
CCLK
INIT
D0-D7
1 T_IC
2 T_DC
BYTE
0
BYTE
1
T_CD 3
BYTE
2
BYTE
3
Header
BYTE
4
BYTE
5
BYTE
6
BYTE
A
BYTE
B
BYTE
C
DOUT
Header Loaded
First FPGA Filled
CS1
First
FPGA
CS1
Second
FPGA
CS1 all
downstream
FPGAs
Byte A is first frame byte for first FPGA
Byte B is last frame byte for first FPGA
Byte C is first frame byte for second FPGA
99012600
Note: CS1 must remain High throughout loading of the configuration data stream. In the pseudo daisy chain of Figure 5, the 7 byte
data stream header is loaded into all devices simultaneously. Each device’s data frames are then loaded in turn when its
CS1 pin is driven High by the DOUT of the preceding device in the chain.
Figure 6: Express Mode Configuration Switching Waveforms
Data Stream Format
The data stream (“bitstream”) format is identical for all
serial configuration modes, but different for the
4000XLA/XV Express mode. In Express mode, the device
becomes active when DONE goes High, therefore no
length count is required. Additionally, CRC error checking is
not supported in Express mode. The data stream format is
shown in Table 9. Express mode data is shown with D0 at
the left and D7 at the right.
The configuration data stream begins with two bytes of
eight ones each, a preamble code of one byte, followed by
three bytes of eight ones each, and finally an end-of-
header field check byte. This header of seven bytes is fol-
lowed by the actual configuration data in frames. The
length and number of frames depends on the device type.
Each frame begins with a start field and ends with an
end-of-frame field check byte. In all cases, additional
start-up bytes of data are required to provide six, or more,
clocks for the start-up sequence at the end of configuration.
Long daisy chains require additional startup bytes to shift
the last data through the chain. All startup bytes are
don’t-cares; these bytes are not included in bitstreams cre-
ated by the Xilinx software.
A selection of CRC or non-CRC error checking is allowed
by the bitstream generation software. The 4000XLA
Express mode only supports non-CRC error checking. The
non-CRC error checking tests for a designated
end-of-frame field check byte for each frame. non-CRC
error checking tests for a designated end-of-frame field
check byte for each frame.
Table 9: 4000XLA/XV Express Mode Data Stream
Format
Data Type
Fill Byte
Preamble Code
Fill Byte
End-of-Header
Field Check Byte
Start Field
Data Frame
End-of-Frame
Field Check Byte
Extend Write Cycle
Start-Up Bytes
LEGEND:
Express Mode
(D0-D7)
(4000XLA only)
FFFFh
11110010b
FFFFFFh
11010010b
11111110b
DATA(n-1:0)
11010010b
FFD2FFFFFFh
FFFFFFFFFFFFh
Unshaded
Light
Once per data stream
Once per data frame
Detection of an error results in the suspension of data load-
ing and the pulling down of the INIT pin. The user must
detect INIT and initialize a new configuration by pulsing the
PROGRAM pin Low or cycling VCC.
6-166
DS015 (v1.3) October 18, 1999 - Product Specification