XC4036XLA Datasheet, PDF (1/14 Pages) Xilinx, Inc – XC4000XLA/XV Field Programmable Gate Arrays

0
XC4000XLA/XV Field Programmable
R
Gate Arrays
DS015 (v1.3) October 18, 1999
0 0* Product Specification
XC4000XLA/XV Family Features
Electrical Features
Note: XC4000XLA devices are improved versions of • XLA Devices Require 3.0 - 3.6 V (VCC)
XC4000XL devices. The XC4000XV devices have the • XV Devices Require 2.3- 2.7 V (VCCINT)
same features as XLA devices, incorporate additional inter-
and 3.0 - 3.6 V (VCCIO)
connect resources and extend gate capacity to 500,000 • 5.0 V TTL compatible I/O
system gates. The XC4000XV devices require a separate • 3.3 V LVTTL, LVCMOS compliant I/O
2.5V power supply for internal logic but maintain 5V I/O • 5.0 V and 3.0 V PCI Compliant I/O
compatibility via a separate 3.3V I/O power supply. For • 12 mA or 24 mA Current Sink Capability
additional information about the XC4000XLA/XV device • Safe under All Power-up Sequences
architecture, refer to the XC4000E/X FPGA Series general • XLA Consumes 40% Less Power than XL
and functional descriptions.
• XV Consumes 65% Less Power than XL
• System-featured Field-Programmable Gate Arrays
• Optional Input Clamping to VCC (XLA) or VCCIO (XV)
- Select-RAM^TM memory: on-chip ultra-fast RAM with
- Synchronous write option
Additional Features
- Dual-port RAM option
• Footprint Compatible with XC4000XL FPGAs - Lower
- Flexible function generators and abundant flip-flops
cost with improved performance and lower power
6
- Dedicated high-speed carry logic
• Advanced Technology — 5 layer metal, 0.25 µm CMOS
- Internal 3-state bus capability
process (XV) or 0.35 µm CMOS process (XLA)
- Eight global low-skew clock or signal distribution
• Highest Performance — System erformance beyond
networks
100 MHz
• Flexible Array Architecture
• High Capacity — Up to 500,000 system gates and
• Low-power Segmented Routing Architecture
270,000 synchronous SRAM bits
• Systems-oriented Features
• Low Power — 3.3 V/2.5 V technology plus segmented
- IEEE 1149.1-compatible boundary scan
routing architecture
- Individually programmable output slew rate
• Safe and Easy to Use — Interfaces to any combination
- Programmable input pull-up or pull-down resistors
of 3.3 V and 5.0 V TTL compatible devices
- Unlimited reprogrammability
• Read Back Capability
- Program verification and internal node observability
*_{Table 1: XC4000XLA Series Field Programmable Gate Arrays}
Device
Logic
Cells
Max Logic Max. RAM
Typical
Gates
Bits
Gate Range
(No RAM) (No Logic) (Logic and RAM)*
XC4013XLA
1,368
13,000
18,432 10,000 - 30,000
XC4020XLA
1,862
20,000
25,088 13,000 - 40,000
XC4028XLA
2,432
28,000
32,768 18,000 - 50,000
XC4036XLA
3,078
36,000
41,472 22,000 - 65,000
XC4044XLA
3,800
44,000
51,200 27,000 - 80,000
XC4052XLA
4,598
52,000
61,952 33,000 - 100,000
XC4062XLA
5,472
62,000
73,728 40,000 - 130,000
XC4085XLA
7,448
85,000 100,352 55,000 - 180,000
XC40110XV
9,728
110,000 131,072 75,000 - 235,000
XC40150XV
12,312
150,000 165,888 100,000 - 300,000
XC40200XV
16,758
200,000 225,792 130,000 - 400,000
XC40250XV
20,102
250,000 270,848 180,000 - 500,000
* Maximum values of gate range assume 20-30% of CLBs used as RAM
CLB
Matrix
24 x 24
28 x 28
32 x 32
36 x 36
40 x 40
44 x 44
48 x 48
56 x 56
64 x 64
72 x 72
84 x 84
92 x 92
Total
CLBs
576
784
1,024
1,296
1,600
1,936
2,304
3,136
4,096
5,184
7,056
8,464
Number
of
Flip-Flops
1,536
2,016
2,560
3,168
3,840
4,576
5,376
7,168
9,216
11,520
15,456
18,400
Max.
User I/O
192
224
256
288
320
352
384
448
448
448
448
448
Required
Configur-
ation Bits
393,632
521,880
668,184
832,528
1,014,928
1,215,368
1,433,864
1,924,992
2,686,136
3,373,448
4,551,056
5,433,888
DS015 (v1.3) October 18, 1999 - Product Specification
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