WP358 Datasheet, PDF (7/10 Pages) Xilinx, Inc – Simplifying Embedded

Using and Modifying the Embedded Targeted Reference Design
Using and Modifying the Embedded Targeted Reference Design
The embedded targeted reference design is the starting point for embedded hardware
and software design with the Spartan-6 and Virtex-6 Embedded kits. The key steps in
using the embedded targeted reference design are:
• Hardware modifications
• Software modifications and programming
• Integrating the design
• Profiling and debugging
Hardware Modifications
Before modifying the MicroBlaze PSS, the exact system configuration can be seen in
the MicroBlaze PSS data sheet included in the embedded kits. This data sheet provides
a traditional processor-centric view of the system in terms of block diagrams, address
maps, external ports, and design clock frequencies. The MicroBlaze PSS is provided in
the embedded kit as an XPS project that can be configured graphically using the XPS
IDE. When the XPS design is opened, a system assembly panel allows viewing of the
system topology between the MicroBlaze processor and the IP blocks included in the
PSS. By double-clicking on the MicroBlaze processor, various processor parameters
like caches and MMU configuration can be modified. In addition, by double-clicking
on the clockgen block, features such as the system clock frequencies for the processor
and memory interfaces can be modified quickly.
XPS includes a comprehensive catalog of industry-standard IP cores from simple
general-purpose parallel I/O cores to the high-performance Gigabit Ethernet MAC IP
core. Within XPS, IP can be included by dragging and dropping any of the available
peripheral IPs into the system. The system assembly view then enables connection of
the IP to the MicroBlaze PSS. The address of the included peripheral can be assigned in
the address map tab of the system assembly view. Navigation to the ports tab then
enables I/O signal connection of the IP core to the external FPGA pins. This last step is
done to assign pin constraints to the external pins of the added peripherals.
XPS provides a Create IP wizard to assist in the creation of custom embedded IP that
can be interfaced to the MicroBlaze PSS. The embedded kit contains some example
user IP, and the steps for creating them are described in the hardware tutorial. In
addition, designers can import their own IP in the XPS pcore standard, or IP from the
Xilinx partner ecosystem.
After the embedded processing system is modified, the design is ready to be
transferred to the FPGA. Many details of the FPGA implementation flow are
abstracted in the XPS design environment. By clicking on the Generate Netlist button,
the tools automatically generate RTL wrappers for each IP, create the bus connections,
generate the synthesis scripts, and call the synthesis tools to generate the netlist.
Similarly, by clicking on the Generate Bitstream button, the underlying FPGA
implementation tools are automatically called to generate the FPGA design bitstream.
Software Development Flow
Before developing any software, the MicroBlaze system configuration can be seen in
the MicroBlaze PSS data sheet included in the embedded kits. The pre-configured
MicroBlaze PSS is the starting point for software development with the embedded
kits.
WP358 (v1.0) December 8, 2009
www.xilinx.com
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