WP358 Datasheet, PDF (5/10 Pages) Xilinx, Inc – Simplifying Embedded

The Embedded Targeted Reference Design Features
linear (parallel) flash, 8 MB serial flash, compact flash using the System ACE™
technology, and 1 KB IIC EEPROM is included in the design.
The general-purpose I/O (GPIO) uses the Xilinx Platform Studio (XPS) GPIO IP core
provided with EDK and is instantiated three times in the system to enable a variety of
uses such as control pushbuttons, DIP switches, and LEDs on the associated
development boards that run the design.
The Tri-Mode Ethernet MAC (TEMAC) core is configured to support a GMII/MII
PHY interface and contains internal 4 KB transmit and receive FIFOs. The TEMAC
core can run at 10 Mb/s, 100 Mb/s, or 1,000 Mb/s depending on the network to which
it is attached.
For timers, the XPS Timer core delivered with the EDK tool suite is configured to
provide two 32-bit timers. For serial communication, there is an integrated
16550-compatible UART core that is pre-configured to use interrupts. The baud rate,
data bits, and parity settings of this UART core are controlled by software.
The features of the MicroBlaze Processor Sub-system are summarized here:
• Processor Block:
• 32-bit MicroBlaze processor with 8 KB I cache and 8 KB D cache, consisting of:
- Hardware barrel shifter
- Memory management unit
(The MicroBlaze processor and system bus run at 100 MHz)
• 8 KB local memory for instructions and data
• Debug module
• Interrupt controller
• Dual 32-bit timer/counter
• Memory:
• 128 MB DDR3 SDRAM interface operating at 400 MHz
• 32 KB internal block RAM
• 32 MB linear (parallel) flash
• 8 MB serial flash
• Compact flash using System ACE™ technology
• 1 KB IIC EEPROM
• Multi-port memory controller with one available port for the user logic interface to
the external DDR3 SODIMM memory
• I/O:
• Three GPIO controllers
• 16550 UART core
• 10/100/1000 TEMAC core
• Serial Peripheral Interface (SPI) and Inter-Integrated Circuit (I²C) serial interface cores
WP358 (v1.0) December 8, 2009
www.xilinx.com
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