WP358 Datasheet, PDF (4/10 Pages) Xilinx, Inc – Simplifying Embedded

The Embedded Targeted Reference Design Features
X-Ref Target - Figure 2
Flash
(32 MB)
Compact
Flash
SPI
Flash
IIC
EEPROM
DDR3
(128 MB)
MicroBlaze Processor Sub-System
Memory
Processor Block
Input/Output
Flash/SRAM
Controller
SysACE
Compact Flash
Controller
SPI Flash
Controller
IIC EEPROM
Controller
Multiport Internal
Memory Block RAM
Controller (32 KB)
Internal RAM
(8 KB)
MicroBlaze
8 KB I and D Caches
MMU
Dual
Timer/Counter
Interrupt
Controller
GPIO
GPIO
GPIO
UART
16550
Tri-Mode
Ethernet
MAC
User Access to
External Memory
User Access to
Internal Memory
User Interrupts
LEDs
Buttons
Switches
RS-232
Line Driver/
Receiver
Ethernet
PHY
Configurable User Logic
XC6SLX45T
WP358_02_120509
Figure 2: MicroBlaze Processor Sub-System within the FPGA
The Embedded Targeted Reference Design Features
The MicroBlaze processor is configured with a Memory Management Unit (MMU)
and various parameters optimized for performance, including the 5-stage pipeline
option (as opposed to the slower 3-stage pipeline option) and a hardware barrel
shifter. The hardware barrel shifter can shift or rotate a data word by any number of
bits in a single clock cycle. Data shifting is a required element of many key operations
such as address generation and arithmetic functions. The action of a barrel shifter can
be emulated in software, but this takes valuable time not available in real-time
applications. The instruction cache and data cache are both enabled, each with a cache
size of 8 KB.
The MMU is configured in Virtual mode with two memory protection zones to run
full-fledged embedded operating systems like Linux. In Virtual mode, the MMU
controls effective address-to-physical address mapping and supports memory
protection. Virtual mode provides greater control over memory protection. The MMU
provides memory protection and relocation, which are useful for multi-tasking
environments. Multi-tasking gives the appearance of simultaneous or
near-simultaneous execution of multiple programs.
For memory support, a variety of features are pre-configured to support various types
of memory devices. The Multi-Port Memory Controller (MPMC), also delivered with
the EDK tool suite, is configured to provide four 32-bit bidirectional ports for access to
the external DDR3 memory. In addition, support for 32 KB internal block RAM, 32 MB
4
www.xilinx.com
WP358 (v1.0) December 8, 2009