WP358 Datasheet, PDF (3/10 Pages) Xilinx, Inc – Simplifying Embedded

The Embedded Targeted Reference Design
the completeness of the MicroBlaze PSS, one must appreciate the current method of
making those setup decisions in developing and using a processor system in an FPGA.
To start with, the base processor used in the MicroBlaze PSS is the 32-bit Xilinx
MicroBlaze processor CPU core. The MicroBlaze processor core is a parameterizable IP
block delivered by Xilinx in the Embedded Development Kit (EDK) tool suite that
offers various options that users might want to configure. Selectable features include
enabling instruction and/or data caches as well as the sizes of the caches. The user can
also configure and add features such as a hardware multiplier, hardware divide
function, barrel shifter, memory management unit, and an IEEE floating point
coprocessor to the MicroBlaze processor block. While this flexibility delivers optimum
feature, performance, and area (cost) trade-offs, actually creating the design takes
some effort that might not be required. At this first step, the MicroBlaze PSS design has
made those decisions that are suitable for a variety of applications and is ready to use
without any further configuration.
The processor core is the basic foundation for embedded processing use. To be useful,
it must have some basic support (such as reset and interrupt circuits) as well as key
peripherals and interconnects that are required in many applications. Basic
peripherals such as memory controllers, timers, interrupt controllers, and serial
interfaces are all available to be configured and added within the framework of the
EDK tool suite. The challenge here is that one might not want to spend time
configuring these basic peripherals (and the settings associated with them) but
instead, just use them. Here again, the MicroBlaze PSS has been pre-configured to use
a basic set of peripherals for most applications. The result is a pre-configured
embedded processing system that is ready to be programmed, as illustrated in
Figure 1.
X-Ref Target - Figure 1
MicroBlaze Processor Sub-System
Memory
Processor Block
Input/Output
Flash/SRAM
Controller
SysACE
Compact Flash
Controller
SPI Flash
Controller
IIC EEPROM
Controller
Multiport Internal
Memory Block RAM
Controller (32 KB)
Internal RAM
(8 KB)
MicroBlaze
8 KB I and D Caches
MMU
Dual
Timer/Counter
Interrupt
Controller
GPIO
GPIO
GPIO
UART
16550
Tri-Mode
Ethernet
MAC
WP358_01_120509
Figure 1: MicroBlaze Processor Sub-System
With this basic system configuration, designers can start evaluating, programming, or
both, for their application development. In addition, from an FPGA hardware
perspective, designers can use this targeted reference design as the core of their
complete system design, as shown in Figure 2. The user-defined portion of the logic in
Figure 2 is where the hardware designer can customize and extend the targeted
reference design using the Xilinx EDK tool suite. It is for this reason that Xilinx has
named this design the MicroBlaze Processor Sub-System, because it truly is a
sub-system to be used in a more robust system driven by application requirements.
WP358 (v1.0) December 8, 2009
www.xilinx.com
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