DS848 Datasheet, PDF (7/9 Pages) Xilinx, Inc – LogiCORE IP Virtex-6 FPGA Triple-Rate SDI v1.0

LogiCORE IP Virtex-6 FPGA Triple-Rate SDI v1.0
receiver also captures SMPTE 352 payload ID packets from data stream 1 and outputs the captured user data words
on dedicated output ports.
If the incoming 3G-SDI signal conforms to SMPTE 425 level B, the Triple-Rate SDI receiver outputs four 10-bit data
streams at a nominal rate of 74.25 MHz or 74.25/1.001 MHz. The receiver checks for CRC errors on all four data
streams and captures and outputs the line numbers from the A-Y and B-Y data streams. It also captures and outputs
SMPTE 352 packets from both the A data stream pair and the B data stream pair. The user data words from the
captured SMPTE 352 packet can be used to determine if the four data streams are compliant with SMPTE 425 level
B-DL (dual link) or level B-DS (dual stream). If they are compliant with level B-DL, the data streams carry a single
video stream mapped per the SMPTE 372 standard. If they are compliant with level B-DS, data streams carry two
separate HD-SDI compatible video streams that were aggregated on a single 3G-SDI signal.
Triple-Rate SDI Transmitter Overview
The Triple-Rate SDI transmitter supports all five supported SDI bit rates, requiring just two different GTX reference
clock frequencies to do so. Table 3 shows the supported GTX reference clock frequencies for each bit rate. If
148.5 MHz is used for one reference clock frequency, 148.5/1.001 MHz must be used for the other. Or, if 74.25 MHz
is used for one reference clock frequency, 74.25/1.001 MHz must be used for the other. The two reference clock
frequencies can be input to the FPGA as one reference clock, using an external switch or a clock generator that can
produce either required reference clock frequency or as two separate reference clocks, one of each frequency, using
the clock multiplexer built into the GTX transceiver to switch between the two reference clocks.
Table 3: Triple-Rate SDI TX GTX Reference Clock Frequencies
SDI Mode
Bit Rate
Required GTX TX REFCLK Frequency
SD-SDI
270 Mb/s
148.5 MHz or 74.25 MHz
HD-SDI
1.485 Gb/s
1.485/1.001 Gb/s
148.5 MHz or 74.25 MHz
148.5/1.001 MHz or 74.25/1.001 MHz
3G-SDI
2.97 Gb/s
2.97/1.001 Gb/s
148.5 MHz or 74.25 MHz
148.5/1.001 MHz or 74.25/1.001 MHz
The SDI mode (SD-SDI, HD-SDI, or 3G-SDI) in which the Triple-Rate SDI transmitter is operating is controlled by
an input port. Thus, the transmitter can be dynamically switched between SDI modes. In turn, the Triple-Rate SDI
transmitter controls the GTX transmitter through the DRP port to configure the GTX transmitter appropriately for
each SDI mode.
The Triple-Rate SDI transmitter can generate and insert SMPTE 352 payload ID packets in any SDI mode. The
application must supply the four user data words of the SMPTE 352 packet to the transmitter, and the transmitter
formats and inserts the packet appropriately.
Operation of the Triple-Rate SDI Transmitter in SD-SDI Mode
In SD-SDI mode, the GTX transmitter is configured to run at a line rate of 2.97 Gb/s. The Triple-Rate SDI transmitter
takes in a 10-bit data stream at a 27 MHz rate, optionally calculates and inserts SMPTE RP-168 EDH packets,
scrambles the data, and then replicates each bit of the 270 Mb/s bitstream 11 times before sending the data to the
GTX transmitter. Because the line rate of the GTX transmitter is 11 times the 270 Mb/s bit rate of the SD-SDI signal
and the data provided to the GTX transmitter by the Triple-Rate SDI transmitter has each bit replicated 11 times, the
resulting bitstream output by the GTX transmitter is a valid 270 Mb/s SD-SDI bitstream.
The EDH generation and insertion function does make the Triple-Rate SDI transmitter larger. However, if this
function is not required, it can be optimized out of the design by permanently disabling EDH insertion.
DS848 June 22, 2011
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Product Specification