DS848 Datasheet, PDF (2/9 Pages) Xilinx, Inc – LogiCORE IP Virtex-6 FPGA Triple-Rate SDI v1.0

LogiCORE IP Virtex-6 FPGA Triple-Rate SDI v1.0
Applications
• Professional broadcast equipment
• Medical imaging
Resource Utilization
Table 1 lists the resource usage for the LogiCORE IP Virtex-6 FPGA Triple-Rate SDI core.
Table 1: Resource Usage
RX only without EDH
LUTs
Flip-Flops
Slices⁽¹⁾
BUFG/BUFR
Transceivers
RX only with EDH
LUTs
Flip-Flops
Slices⁽¹⁾
BUFG/BUFR
Transceivers
TX only without EDH
LUTs
Flip-Flops
Slices⁽¹⁾
BUFG/BUFR
Transceivers
TX only with EDH
LUTs
Flip-Flops
Slices⁽¹⁾
BUFG/BUFR
Transceivers
RX/TX without RX EDH with TX EDH
LUTs
Flip-Flops
Slices⁽¹⁾
BUFG/BUFR
Transceivers
RX/TX with RX and TX EDH
LUTs
Flip-Flops
Slices⁽¹⁾
BUFG/BUFR
Transceivers
1700
1300
470
1⁽²⁾
1 GTX
2200
1700
590
1⁽²⁾
1 GTX
650
540
185
1⁽²⁾
1 GTX
1200
900
325
1⁽²⁾
1 GTX
2250
1660
620
2⁽²⁾
1 GTX
3150
2400
900
2⁽²⁾
1 GTX
1. Slice counts are only estimates. The exact number of slices depends on level of resource sharing with adjacent logic.
2. Generally, one global or regional clock is used per RX or TX interface. However, an additional global clock is required
to drive the DRPCLK. But, the DRPCLK can be any clock frequency available in the FPGA that falls within the
supported DRPCLK frequency range. Multiple SDI interfaces can share the same global DRPCLK.
DS848 June 22, 2011
www.xilinx.com
2
Product Specification