DS848 Datasheet, PDF (5/9 Pages) Xilinx, Inc – LogiCORE IP Virtex-6 FPGA Triple-Rate SDI v1.0

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Figure 1: Triple-Rate SDI RX/TX Functional Overview
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Notes relevant to Figure 1:
1. The required SDI cable driver and cable equalizer are external to the FPGA.
2. The optional ANC packet insertion function is not included in the Virtex-6 FPGA Triple-Rate SDI core.
Combined with a GTX transceiver, the Virtex-6 FPGA Triple-Rate SDI core implements a complete SD-SDI, HD-SDI,
and 3G-SDI receiver and/or transmitter interface. The GTX receiver interfaces to the SDI connector through an
industry-standard SDI cable equalizer. The GTX transmitter interfaces to the SDI connector through an
industry-standard SDI cable driver.
Triple-Rate SDI Receiver Overview
The Triple-Rate SDI receiver uses a single GTX reference clock frequency to receive all five supported SDI bit rates.
The receiver automatically determines the incoming SDI bit rate and configures itself and the GTX transceiver
appropriately for that SDI mode. The supported GTX receiver reference clock frequencies are: 148.5 MHz,
148.5/1.001 MHz, 74.25 MHz, and 74.25/1.001 MHz. Any of these frequencies can be used, but only a single
frequency is required. The receiver constantly indicates, on dedicated output ports, which SDI mode (SD-SDI,
HD-SDI, or 3G-SDI) is currently being received. For HD-SDI and 3G-SDI, it also reports which of the two bit rates
DS848 June 22, 2011
www.xilinx.com
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Product Specification