DS880 Datasheet, PDF (6/7 Pages) Xilinx, Inc – Video Broadcaster v1.00a

Video Broadcaster v1.00a
Guidelines on Driving s_axis_tvalid
Once s_axis_tvalid is asserted, no interface signals (except the Video Broadcaster core driving
s_axis_tready) may change value until the transaction completes (s_axis_tready and s_axis_tvalid are
high on the rising edge of aclk). Once asserted, s_axis_tvalid may only be de-asserted after a transaction has
completed. Transactions may not be retracted or aborted. In any cycle following a transaction, s_axis_tvalid
can either be de-asserted or remain asserted to initiate a new transfer.
X-Ref Target - Figure 4
Figure 4: Example of READY/VALID Handshake, Start of a New Frame
Guidelines on Driving m[nn]_axis_tready
The m[nn]_axis_tready signal may be asserted before, during or after the cycle in which the Video Broadcaster
core asserted m[nn]_axis_tvalid. The assertion of m[nn]_axis_tready may be dependent on the value of
m[nn]_axis_tvalid. A slave that can immediately accept data qualified by m[nn]_axis_tvalid, should
pre-assert its m[nn]_axis_tready signal until data is received. Alternatively, m[nn]_axis_tready can be
registered and driven the cycle following VALID assertion. It is recommended that the AXI4-Stream slave should
drive READY independently, or pre-assert READY to minimize latency.
Start of Frame Signals - m[nn]_axis_tuser, s_axis_tuser
The Start-Of-Frame (SOF) signal, physically transmitted over the AXI4-Stream TUSER signal, marks the first pixel of
a video frame. The SOF pulse is 1 valid transaction wide, and must coincide with the first pixel of the frame, as seen
in Figure 4. The SOF signal serves as a frame synchronization signal, which allows downstream cores to re-initialize
and detect the first pixel of a frame. The SOF signal may be asserted an arbitrary number of aclk cycles before the
first pixel value is presented on DATA, as long as a VALID/READY is not asserted.
End of Line Signals - m[nn]_axis_tlast, s_axis_tlast
The End-Of-Line (EOL) signal, physically transmitted over the AXI4-Stream TLAST signal, marks the last pixel of a
line. The EOL pulse is 1 valid transaction wide, and must coincide with the last pixel of a scan-line.
Support
Xilinx provides technical support for this LogiCORE IP product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
DS880 October 16, 2012
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Product Specification