DS880 Datasheet, PDF (4/7 Pages) Xilinx, Inc – Video Broadcaster v1.00a

X-Ref Target - Figure 3
!8) 3TREAM
3LAVEINBOUND
INTERFACE
#ORE#LOCK
AND2ESET
Video Broadcaster v1.00a
AXIS?VBROADCASTER
S?AXIS?TVALID
S?AXIS?TDATA
S?AXIS?TLAST
S?AXIS?TUSER
S?AXIS?TREADY
ACLK
ARESETN
M?AXIS?TVALID
M?AXIS?TDATA
M?AXIS?TLAST
M?AXIS?TUSER
M?AXIS?TREADY
M?AXIS?TVALID
M?AXIS?TDATA
M?AXIS?TLAST
M?AXIS?TUSER
M?AXIS?TREADY
!8) 3TREAM
-ASTER;=OUTBOUND
INTERFACE
!8) 3TREAM
-ASTER;=OUTBOUND
INTERFACE
M?AXIS?TVALID
M?AXIS?TDATA
M?AXIS?TLAST
M?AXIS?TUSER
M?AXIS?TREADY
!8) 3TREAM
-ASTER;=OUTBOUND
INTERFACEOPTIONAL
8
Figure 3: Video Broadcaster Core Top-Level Signaling Interface
Common Interface Signals
Table 2 summarizes the signals which are either shared by, or not part of the dedicated AXI4-Stream data control
interfaces.
Table 2: Common Interface Signals
Signal Name Direction Width
Description
aclk
In
1 Video core clock
aresetn
In
1 Video core Active Low synchronous reset
The aclk and aresetn signals are shared between the core and the AXI4-Stream data interfaces.
aclk
The AXI4-Stream interface must be synchronous to the core clock signal aclk. All AXI4-Stream interface’s input
signals are sampled on the rising edge of aclk. All AXI4-Stream output signal’s changes occur after the rising edge
of aclk.
DS880 October 16, 2012
www.xilinx.com
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Product Specification