DS878 Datasheet, PDF (6/8 Pages) Xilinx, Inc – LogiCORE IP ChipScope Pro IBERT for 7 Series GTZ Transceivers (v2.0)

LogiCORE IP ChipScope Pro IBERT for 7 Series GTZ Transceivers (v2.0)
Reference Clock
The reference clock source should be provided for all the serial transceivers selected. The drop-down list provides
you with possible sources based on local clocks in the same quad and shared clocks from north/south OCTALs.
Generating the Core
After entering the IBERT core parameters, click Generate to create the IBERT core files. After the IBERT core has
been generated, a list of files that are generated appears in a separate window called "Readme <corename>."
IBERT Interface Ports
The I/O signals of the IBERT core consist only of the GTZ transceiver reference clocks, the GTZ transceiver transmit
and receive pins, and a system clock (optional). Table 1 lists the IBERT interface ports and their descriptions.
Table 1: Interface Ports
Port Name
Direction
Description
SYSCLK_I
In
Clock that clocks all communication logic. This port is present only when an
external clock is selected in the generator.
TXN_0[7:0]
TXP_0[7:0]
Transmit differential pairs for each of the n GTZ transceivers used.
Out
RXN_0[7:0]
RXP_0[7:0]
Receive differential pairs for each of the n GTZ transceivers used.
In
GTREFCLK0N_I[1:0]
GTREFCLK0P_I[1:0]
GTZ transceiver reference clocks 0 used.
In
The number of MGTREFCLK ports can be equal to or less than the number of
transmit and receive ports because some GTZ transceivers can share clock
inputs.
GTREFCLK1N_I[1:0]
GTREFCLK1P_I[1:0]
GTZ transceiver reference clocks 1 used.
In
The number of MGTREFCLK ports can be equal to or less than the number of
transmit and receive ports because some GTZ transceivers can share clock
inputs.
Performance and Resource Utilization
Table 2 shows the performance and resource utilization numbers generated for the various IBERT setup listed and
targeted to XC7VH580T-HCG1155-2.
Table 2: Performance and Resource Utilization for XC7VH580T-HCG1155-2 Device
IBERT Setup
Resources
Line Rate (Gb/s)
Refclk
Frequency (MHz)
No. of Octal
LUTs
Flip-Flops Block RAMs
27.953
291.172
1
15,543
18,474
0
10.313
322.266
1
15,543
18,474
0
Performance
F_Max (MHz)
149.815
149.815
Verification
Xilinx has verified the IBERT core in a proprietary test environment, using an internally developed bus functional
model.
DS878 December 18, 2012
www.xilinx.com
6
Product Specification