DS878 Datasheet, PDF (4/8 Pages) Xilinx, Inc – LogiCORE IP ChipScope Pro IBERT for 7 Series GTZ Transceivers (v2.0)

LogiCORE IP ChipScope Pro IBERT for 7 Series GTZ Transceivers (v2.0)
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Figure 2: GTZ Internal Clocking Architecture
Pattern Generation and Checking
Each GTZ transceiver enabled in the IBERT design has a pattern generator and a pattern checker. The pattern
generator sends data out through the transmitter. The pattern checker accepts data through the receiver and checks
it against an internally generated pattern. IBERT offers PRBS 7-bit, PRBS 15-bit, PRBS 23-bit, PRBS31-bit, Clk 2x
(101010...), and Clk 10x(11111111110000000000...) patterns.
These patterns are optimized for the logic width that was selected at run time. The TX pattern and RX pattern are
individually selected.
The Analyzer software displays a “link” signal until there are five consecutive cycles with errors. Using the pattern
checker logic, the incoming data is compared against a pattern that is internally generated. When the checker
receives five consecutive cycles of data with errors, the ChipScope Pro Analyzer software disables the link signal.
Internal counters accumulate the number of words and errors received.
DRP and Port Access
You can change GTZ transceiver ports and attribute values. The DRP interface logic allows the run-time software to
monitor and change any attribute in the GTZ OCTAL. When applicable, readable and writable registers are also
included that are connected to the many ports of the GTZ OCTAL. All are accessible at run-time using the
ChipScope Analyzer tool.
Vivado IP Catalog
The Vivado IP Catalog allows you to define and generate a customized IBERT core to use to validate the
transceivers of the device. You can customize the number of serial transceivers within the OCTAL that are power
up, and the line rate and reference clock for the OCTAL.
DS878 December 18, 2012
www.xilinx.com
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Product Specification