DS878 Datasheet, PDF (3/8 Pages) Xilinx, Inc – LogiCORE IP ChipScope Pro IBERT for 7 Series GTZ Transceivers (v2.0)

X-Ref Target - Figure 1
LogiCORE IP ChipScope Pro IBERT for 7 Series GTZ Transceivers (v2.0)
6IRTEX &0'!8#6(4
'4:/#4!,
,ANE
,ANE
,ANE
,ANE
,ANE
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'4:
#HANNELS

'4:
3,2
#HANNELS

'4:
#HANNELS

'4:
3,2
#HANNELS

Figure 1: GTZ OCTAL in a Virtex-7 FPGA XC7VH580T
The serial transceiver REFCLK can be sourced from CPLL based on multiplexers as shown in Figure 2. This can be
selected from the 7 series FPGA IBERT IP Catalog GUI.
Each OCTAL has two REFCLK inputs and attributes control which REFCLK is used for each channel. The IBERT 7
series GTZ core only supports one line rate per OCTAL.
DS878 December 18, 2012
www.xilinx.com
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Product Specification