DS878 Datasheet, PDF (5/8 Pages) Xilinx, Inc – LogiCORE IP ChipScope Pro IBERT for 7 Series GTZ Transceivers (v2.0)

LogiCORE IP ChipScope Pro IBERT for 7 Series GTZ Transceivers (v2.0)
Entering the Component Name
The Component Name field, stored as component_name in the generated XCO parameter file, can consist of any
combination of alpha-numeric characters including the underscore symbol. However, the underscore symbol
cannot be the first character in the component name.
Generating an Example Design
The IBERT Vivado IP Catalog normally generates example design along with standard Xilinx Vivado IP Catalog
output files, such as a netlist and instantiation template files. Example design and Implement scripts are generated
under the folder with the component name.
Receiver Output Clock
The receiver clock probe enable is provided to pull out a recovered clock from any serial transceiver, if desired.
When enabled, a new panel appears just before the summary page where you can fill in the serial transceiver source
and probe pin standards.
GTZ Transceiver Naming Style
There are two conventions for naming the GTZ transceiver, based on the location in the serial transceiver tile in the
device. M and n in XmYn naming convention indicate the X and Y coordinates of the serial transceiver location. M
and n in serial transceiver m_n naming convention indicating serial transceiver number and quad associated.
System Clock
The IBERT core requires a free-running system clock for communication and other logic that is included in the core.
This clock can be chosen at generation time to originate from an FPGA pin, or to be driven from the TXOUTCLK
port of one of the GTZ transceivers. In order for the core to operate properly, this system clock source must remain
operational and stable when the FPGA is configured with the IBERT core design. If the system clock is running
faster than 100 MHz, it is divided down internally using an Mixed-Mode Clock Manager (MMCM) to satisfy timing
constraints. Note that the clock source selected must be stable and free running after the FPGA is configured with
the IBERT design. The system clock is used for core communication and as a reference for system measurements.
Therefore, the clock source selected must remain operational and stable when using the IBERT core.
Line Rate Support
IBERT supports one line rate per OCTAL. A list of the supported line rates is available, and for each line rate, one
or more reference clock rates are supported. The proper divider settings is specified for each line rate/refclk rate
combination.
Serial Transceiver Location
Based on the total number of serial transceivers selected, provide the specific location of each serial transceiver that
you intend to use. The region shown in the panel indicates the location of serial transceivers in the tile. This
demarcation of region is based on the physical placement of serial transceivers with respect to median of BUFGs
available for each device. Depending on the device selected, one or two OCTALs are available. The region shown in
the panel indicates the location of the OCTAL in the device.
DS878 December 18, 2012
www.xilinx.com
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Product Specification