DS737 Datasheet, PDF (5/5 Pages) Xilinx, Inc – Wrapper around the MMCM_ADV primitive

Mixed-Mode Clock Manager (MMCM) Module (v1.00a)
Device Utilization and Performance Benchmarks
Core Performance
This module uses one MMCM primitive and one BUFG primitive for each clock input and output that
is buffered.
Specification Exceptions
USB 2.0
Not Applicable.
Reference Documents
1. Virtex-6 User Guide
2. Virtex-6 Libraries Guide for HDL Designs
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in
devices that are not defined in the documentation, if customized beyond that allowed in the product
documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
Revision History
The following table shows the revision history for this document:
Date
6/24/09
Version
1.0
Initial Xilinx release.
Description of Revisions
Notice of Disclaimer
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DS737 June 24, 2009
www.xilinx.com
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Product Specification