DS737 Datasheet, PDF (4/5 Pages) Xilinx, Inc – Wrapper around the MMCM_ADV primitive

Mixed-Mode Clock Manager (MMCM) Module (v1.00a)
Table 2: MMCM Module Input and Output Signals
Signal
Signal
Direction
Default Value
Description
CLKFBOUT
Output
Feedback clock output (typically to be connected
to CLKFBIN)
CLKFBOUTB
Output
Inverted feedback clock output
CLKOUT0...
CLKOUT6
Output
Clock output
CLKOUT0B...
CLKOUT3B
Output
Inverted clock output
LOCKED
Output
MMCM Locked signal
CLKFBSTOPPED
Output
Status pin indicating that the feedback clock has
stopped
CLKINSTOPPED
Output
Status pin indicating that the input clock has
stopped
PSDONE
Output
Phase shift done
CLKFBIN
Input
Clock feedback input
CLKIN1
Input
Primary clock input
RST
PWRDWN
PSCLK
Input
Input
Input
Same as
MMCM_ADV primitive
Asynchronous global reset signal
MMCM global power down pin
Phase shift clock
PSEN
Input
Phase shift enable
PSINCDEC
Input
Phase shift Increment/Decrement control
Register Descriptions
Not Applicable.
Timing Diagrams
See the Virtex-6 User Guide for more information.
Design Constraints
None.
Design Implementation
Target Technology
This module is intended for use on Virtex-6 devices.
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DS737 June 24, 2009
Product Specification