DS737 Datasheet, PDF (1/5 Pages) Xilinx, Inc – Wrapper around the MMCM_ADV primitive

DS737 June 24, 2009
Mixed-Mode Clock Manager
(MMCM) Module (v1.00a)
Product Specification
Introduction
The MMCM primitive in Virtex-6 parts is used to
generate multiple clocks with defined phase and
frequency relationships to a given input clock. The
MMCM module is a wrapper around the MMCM_ADV
primitive that allows the MMCM to be used in the EDK
tool suite.
Features
• Wrapper around the MMCM_ADV primitive
• Configurable BUFG insertion
• Supports all MMCM_BASE and some
MMCM_ADV features, as applicable to embedded
system designs
LogiCORE™ IP Facts
Core Specifics
Supported Device
Family
Virtex^®-6^®
Resources Used
I/O
LUTs FFs
Block
RAMs
N/A
N/A
N/A
N/A
Version of core
1.00a
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Constraints File
None
Verification
None
Instantiation Template
None
Design Tool Requirements
Xilinx Implementation
Tools
ISE® 11x
Verification
ModelSim PE/SE 6.4b or later
Simulation
ModelSim PE/SE 6.4b or later
Synthesis
XST
Support
Provided by Xilinx, Inc.
© 2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
DS737 June 24, 2009
www.xilinx.com
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Product Specification