DS612 Datasheet, PDF (5/8 Pages) Xilinx, Inc – LogiCORE IP OBSAI v5.1

LogiCORE IP OBSAI v5.1
Spartan-6 FPGAs
Table 3 provides approximate device utilization figures for a core configured to support WCDMA framing format
on a Spartan-6 LXT device. The values include the GTPA1 transceiver and clock control logic.
Table 3: Device Utilization - Spartan-6 FPGA
Parameter Values
Device Resources
Mode
Master/
Slave
Include
Ethernet
Include
Generic
Messaging
LUTs
Registers
Block
RAM
(18K)
PLL DCM BUFG BUFIO2
D^RP3
Master
N/A
N/A
1400 1330
1
1
1
5
2
Slave
N/A
N/A
1380 1340
0
1
1
5
2
RP3-01 Master
N
N
2280 1900
1
1
1
5
2
i_Master
Y
N
2750 2490
5
1
1
5
2
s_Master
N
Y
2500 2240
3
1
1
5
2
Slave
N
N
2550 2150
0
1
1
5
2
c_Slave
Y
N
2860 2740
4
1
1
5
2
o ^Slave
N
Y
2620 2480
2
1
1
5
2
Note: All configurations use a single GTPA1 transceiver.
BUFIO2FB
2
2
2
2
2
2
2
2
n _{Kintex-7 and Virtex-7 FPGAs}
t Table 4 provides approximate device utilization figures for a core configured to support WCDMA framing format
i ^{on Kintex-7 and Virtex-7 devices. The values include the GTPA1 transceiver and clock control logic.}
n _{Table 4: Device Utilization - Kintex-7 and Virtex-7 FPGAs}1
Parameter Values
Device Resources
u _Mode
Master/
Slave
Include
Ethernet
Include
Generic
Messaging
LUTs
Block
Registers RAM
(18K)
MMCM
BUFG²
e _RP3
Master
N/A
N/A
1150
1590
1
1
2
Slave
N/A
N/A
1170
1590
0
1
2
d _RP3-01
Master
N
N
2450
2350
1
1
2
Master
Y
N
2860
2960
5
1
2
Master
N
Y
2620
2680
3
1
2
IP _Slave
N
N
2190
2490
0
1
2
BUFR²
1
1
1
1
1
1
Slave
Y
N
2680
3100
4
1
2
1
Slave
N
Y
2360
2820
2
1
2
1
1. All configurations use a single GTXE2 Transceiver.
2. Virtex-7 case, Kintex-7 uses 3 BUFG, 0 BUFR
DS612 March 1, 2011
www.xilinx.com
5
Product Specification