DS612 Datasheet, PDF (4/8 Pages) Xilinx, Inc – LogiCORE IP OBSAI v5.1

LogiCORE IP OBSAI v5.1
Device Utilization
Virtex-5 FPGAs
Table 1 provides approximate device utilization figures for a core configured to support WCDMA framing format
on a Virtex-5 SXT or LXT device. The values include the RocketIO™ transceiver and clock control logic.
Table 1: Device Utilization - Virtex 5 FPGA
Parameter Values
Device Resources
DMode
Master/
Slave
Include
Ethernet
Include
Generic
Messaging
LUTs
Registers
Block
RAM PLL
(18K)
RP3
Master
N/A
N/A
1680
1360
1
1
i^Slave
N/A
N/A
1665
1360
0
1
s _RP3-01
Master
N
N
2700
1930
1
1
Master
Y
N
3250
2520
5
1
c_Master
N
Y
2970
2270
3
1
Slave
N
N
2660
2140
0
1
o _Slave
Y
N
3200
2730
4
1
Slave
N
Y
2930
2480
2
1
n _{Note: All configurations use a single GTP_DUAL tile (FXT/LXT) or GTX_DUAL tile (FXT)}
BUFG
4
4
4
4
4
4
4
4
BUFR
1
1
1
1
1
1
1
1
t _{Virtex-6 FPGAs}
i _{Table 2 provides approximate device utilization figures for a core configured to support WCDMA framing format}
n _{on a Virtex-6 LXT device. The values include the GTXE1 transceiver and clock control logic.}
Table 2: Device Utilization - Virtex 6 FPGA
u _{Parameter Values}
Device Resources
e Mode
Master/
Slave
Include
Ethernet
Include
Generic
Messaging
LUTs
Registers
Block
RAM
(18K)
MMCM
BUFG
BUFR
RP3
Master
N/A
N/A
1790
1340
1
1
4
1
d _Slave
N/A
N/A
1780
1350
0
1
4
1
RP3-01
Master
N
N
2830
1910
1
1
4
1
Master
Y
N
3460
2490
5
1
4
1
IP _Master
N
Y
3140
2240
3
1
4
1
Slave
N
N
2980
2130
0
1
4
1
Slave
Y
N
3580
2710
4
1
4
1
Slave
N
Y
3290
2460
2
1
4
1
Note: All configurations use a single GTXE1 transceiver.
DS612 March 1, 2011
www.xilinx.com
4
Product Specification