DS612 Datasheet, PDF (1/8 Pages) Xilinx, Inc – LogiCORE IP OBSAI v5.1

LogiCORE IP OBSAI v5.1
DS612 March 1, 2011
Product Specification
Introduction
LogiCORE IP Facts
The LogiCORE™ IP OBSAI core implements an OBSAI
RP3 interface supporting RP3-01 at 768 Mb/s, 1.5 Gb/s,
and 3 Gb/s line rates using GTP or GTX transceivers in
Virtex®-5, Spartan®-6 and Virtex-6 FPGAs. 6 Gb/s line
Drate is supported in Virtex-6 devices.
The OBSAI core can be configured as a master or slave
for use in base station or Remote RF Units (RRUs).
is _Features
• Designed to OBSAI RP3 v4.2 specification[Ref 1]
c • Supports CDMA or WCDMA/WiMAX
802.16/LTE framing formats
o • GTP or GTX Transceivers support
768 Mb/s, 1.5 Gb/s, and 3 Gb/s line rates in
Virtex-5 devices
n • GTPA1 Transceivers support 768 Mb/s, 1.5 Gb/s,
and 3 Gb/s line rates in Spartan-6 devices
t _{• GTXE1 Transceivers support 768 Mb/s, 1.5 Gb/s,}
i ^{3 Gb/s and 6 Gb/s line rates in Virtex-6 devices}
n • GTXE2 Transceivers support 768 Mb/s, 1.5 Gb/s,
3 Gb/s and 6 Gb/s line rates in Kintex™-7 and
Virtex-7 devices
u _{• Physical and Data Link Layer functions provided}
• Supports RP1 Ethernet Messages[Ref 2], [Ref 3]
e • Ethernet interface connects directly to
LogiCORE IP MACs
• Supports RP1 Frame Clock Burst Messages
d • Provides dedicated serial interfaces for RP1 frame
clock bursts
• Supports fully configurable Modulo-Index
I ^{transmission rules for RP3-01 message types}
P ^{• Creates and processes Round Trip Time (RTT)}
Supported Device
Family¹
Core Specifics
Virtex-5 LXT/SXT/FXT²
Virtex-6 LXT/SXT/HXT/CXT
Spartan-6 LXT
Virtex-7
Kintex-7
Supported User
Interfaces
AXI4-Lite Control/Status Interface
Resources Used
Configuration
LUTs
FFs
Block
RAMs
Virtex-6 RP3-01 Master,
Ethernet (default)
3460 2490
5
Provided with Core
Documentation
Product Specification
User Guide
Design Files
NGC netlist
Example Design
VHDL
Test Bench
VHDL
Constraints File
User Constraints File (.ucf)
Simulation
Model
VHDL
Tested Design Tools
Design Entry Tools
Simulation³
ISE v13.1 software
Mentor Graphics ModelSim v6.6d
Synthesis Tools
XST 13.1
Support
Provided by Xilinx, Inc.
1. For the complete list of supported devices, see the readme.txt file
messages
for this core.
2. Virtex-5 LX20T FPGA is not supported due to clocking resource
• Creates (Master mode core) or processes (Slave
limitations.
3. Requires a Verilog LRM-IEEE 1364-2005 encryption-compliant
mode core) HW Reset Messages
simulator. For VHDL simulation, a mixed HDL license is required.
• Provides Generic RP3 Messaging interfaces to
support Application Layer messaging
• Supports RP3-01 auto-negotiation
© Copyright 2007- 2011. Xilinx, Inc. XILINX, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries.All other trademarks are the property of their respective owners.
DS612 March 1, 2011
www.xilinx.com
1
Product Specification