XC6VCX75T Datasheet, PDF (43/52 Pages) Xilinx, Inc – Virtex-6 CXT Family Data Sheet

Virtex-6 CXT Family Data Sheet
Table 52: Configuration Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade
-2
-1
Units
BPI Master Flash Mode Programming Switching
T_BPICCO(2)
ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B outputs
6
6
ns
valid after CCLK rising edge at 2.5V
ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B outputs
6
6
ns
valid after CCLK rising edge at 1.8V
T_BPIDCC/T_BPICCD
Setup/Hold on D[15:0] data input pins
T_INITADDR
Minimum period of initial ADDR[25:0] address cycles
SPI Master Flash Mode Programming Switching
4.0/0.0
3
4.0/0.0
3
ns
CCLK cycles
T_SPIDCC/T_SPIDCCD
T_SPICCM
DIN Setup/Hold before/after the rising CCLK edge
3.0/0.0 3.0/0.0
ns
MOSI clock to out at 2.5V
6
6
ns
MOSI clock to out at 1.8V
6
6
ns
T_SPICCFC
FCS_B clock to out at 2.5V
FCS_B clock to out at 1.8V
6
6
ns
6
6
ns
T_FSINIT/T_FSINITH
CCLK Output (Master Modes)
FS[2:0] to INIT_B rising edge Setup and Hold
2
2
µs
T_MCCKL
T_MCCKH
CCLK Input (Slave Modes)
Master CCLK clock Low time duty cycle
Master CCLK clock High time duty cycle
45/55
45/55
45/55
45/55
%, Min/Max
%, Min/Max
T_SCCKL
Slave CCLK clock minimum Low time
T_SCCKH
Slave CCLK clock minimum High time
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
2.5
2.5
ns, Min
2.5
2.5
ns, Min
F_DCK
T_{MMCMDCK_DADDR}/
T_{MMCMCKD_DADDR}
T_{MMCMDCK_DI}/T_{MMCMCKD_DI}
T_{MMCMDCK_DEN}/T_{MMCMCKD_DEN}
T_{MMCMDCK_DWE}/T_{MMCMCKD_DWE}
T_{MMCMCKO_DO}
T_{MMCMCKO_DRDY}
Maximum frequency for DCLK
DADDR Setup/Hold
DI Setup/Hold
DEN Setup/Hold time
DWE Setup/Hold time
CLK to out of DO⁽³⁾
CLK to out of DRDY
200
200
1.63/0.00 1.63/0.00
1.63/0.00 1.63/0.00
1.63/0.00 1.63/0.00
1.63/0.00 1.63/0.00
3.64
3.64
0.38
0.38
MHz
ns
ns
ns
ns
ns
ns
Notes:
1. To support longer delays in configuration, use the design solutions described in Virtex-6 FPGA Configuration Guide.
2. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
3. DO will hold until next DRP operation.
DS153 (v1.6) February 11, 2011
www.xilinx.com
Product Specification
43