XC6VCX75T Datasheet, PDF (41/52 Pages) Xilinx, Inc – Virtex-6 CXT Family Data Sheet

Virtex-6 CXT Family Data Sheet
Table 51: DSP48E1 Switching Characteristics (Cont’d)
Symbol
Description
Clock to Outs from Input Register Clock to Cascading Output Pins
T_{DSPCKO_{ACOUT; BCOUT}_{AREG; BREG}}
T_{DSPCKO_{PCOUT, CARRYCASCOUT,}
MULTSIGNOUT}_{AREG, BREG}_MULT
CLK (AREG, BREG) to {P, CARRYOUT} output
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT} output
using multiplier
T_{DSPCKO_{PCOUT, CARRYCASCOUT,}
MULTSIGNOUT}_{AREG, BREG}
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT} output not
using multiplier
T_{DSPCKO_{PCOUT, CARRYCASCOUT,}
MULTSIGNOUT}_DREG_MULT
T_{DSPCKO_{PCOUT, CARRYCASCOUT,}
MULTSIGNOUT}_CREG
Maximum Frequency
CLK (DREG) to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output using multiplier
CLK (CREG) to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output
F_MAX
F_{MAX_PATDET}
F_{MAX_MULT_NOMREG}
F_{MAX_MULT_NOMREG_PATDET}
With all registers used
With pattern detector
Two register multiply without MREG
Two register multiply without MREG with pattern
detect
F_{MAX_PREADD_MULT_NOADREG}
F_{MAX_PREADD_MULT_NOADREG_PATDET}
F_{MAX_NOPIPELINEREG}
F_{MAX_NOPIPELINEREG_PATDET}
Without ADREG
Without ADREG with pattern detect
Without pipeline registers (MREG, ADREG)
Without pipeline registers (MREG, ADREG)
with pattern detect
Speed Grade
-2
-1
0.89
1.02
5.49
6.31
2.40
2.76
5.38
6.18
2.40
2.76
350
275
350
275
262
227
241
209
292
253
292
253
196
170
184
160
Units
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
DS153 (v1.6) February 11, 2011
www.xilinx.com
Product Specification
41