XCF01S Datasheet, PDF (40/47 Pages) Xilinx, Inc – Platform Flash In-System Programmable

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Platform Flash In-System Programmable Configuration PROMs
Table 14: XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48) (Cont’d)
Pin Name
Boundary-
Scan Order
Boundary-
Scan
Function
Pin Description
48-pin
TSOP
(VO48/
VOG48)
CEO
06
Data Out Chip Enable Output. Chip Enable Output (CEO) is connected
to the CE input of the next PROM in the chain. This output is
Low when CE is Low and OE/RESET input is High, AND the
internal address counter has been incremented beyond its
10
05
Output Enable _{Terminal Count (TC) value or the PROM does not contain any}
blocks that correspond to the selected revision. CEO returns
to High when OE/RESET goes Low or CE goes High.
EN_EXT_SEL
31
REV_SEL0
30
REV_SEL1
29
Enable External Selection Input. When this pin is Low, design
revision selection is controlled by the Revision Select pins.
Data In
When this pin is High, design revision selection is controlled
by the internal programmable Revision Select control bits.
25
EN_EXT_SEL has an internal 50 KΩ resistive pull-up to
V_CCO to provide a logic 1 to the device if the pin is not driven.
Data In Revision Select[1:0] Inputs. When the EN_EXT_SEL is Low,
26
the Revision Select pins are used to select the design
revision to be enabled, overriding the internal programmable
Data In
Revision Select control bits. The Revision Select[1:0] inputs
27
have an internal 50 KΩ resistive pull-up to V_CCO to provide a
logic 1 to the device if the pins are not driven.
BUSY
Busy Input. The BUSY input is enabled when parallel mode
is selected for configuration. When BUSY is High, the internal
address counter stops incrementing and the current data
remains on the data pins. On the first rising edge of CLK after
12
Data In
BUSY transitions from High to Low, the data for the next
address is driven on the data pins. When serial mode or
5
decompression is enabled during device programming, the
BUSY input is disabled. BUSY has an internal 50 KΩ
resistive pull-down to GND to provide a logic 0 to the device
if the pin is not driven.
CLKOUT
TMS
TCK
08
Data Out Configuration Clock Output. An internal Programmable
control bit enables the CLKOUT signal, which is sourced from
either the internal oscillator or the CLK input pin. Each rising
edge of the selected clock source increments the internal
address counter if data is available, CE is Low, and
OE/RESET is High. Output data is available on the rising
07
Output Enable ^{edge of CLKOUT. CLKOUT is disabled if CE is High or}
9
OE/RESET is Low. If decompression is enabled, CLKOUT is
parked High when decompressed data is not ready. When
CLKOUT is disabled, the CLKOUT pin is put into a high-Z
state. If CLKOUT is used, then it must be pulled High
externally using a 4.7 KΩ pull-up to V_CCO.
JTAG Mode Select Input. The state of TMS on the rising edge
–
Mode Select
of TCK determines the state transitions at the Test Access Port
(TAP) controller. TMS has an internal 50 KΩ resistive pull-up
21
to V_CCJ to provide a logic 1 to the device if the pin is not driven.
JTAG Clock Input. This pin is the JTAG test clock. It
–
Clock
sequences the TAP controller and all the JTAG test and
20
programming electronics.
JTAG Serial Data Input. This pin is the serial input to all JTAG
TDI
–
Data In
instruction and data registers. TDI has an internal 50 KΩ
resistive pull-up to V_CCJ to provide a logic 1 to the device if
19
the pin is not driven.
TDO
JTAG Serial Data Output. This pin is the serial output for all
–
Data Out
JTAG instruction and data registers. TDO has an internal
50KΩ resistive pull-up to V_CCJ to provide a logic 1 to the
22
system if the pin is not driven.
48-pin
TFBGA
(FS48/
FSG48)
D2
H4
G3
G4
C1
C2
E2
H3
G1
E6
DS123 (v2.13.1) April 3, 2008
www.xilinx.com
Product Specification
40