XCF01S Datasheet, PDF (20/47 Pages) Xilinx, Inc – Platform Flash In-System Programmable

R
X-Ref Target - Figure 10
VCCJ VCCO VCCINT
External
Oscillator
TDI
TMS
TCK
TDO
V_CCINT
VCCO(2)
VCCJ(2)
D[0:7]
XCFxxP
Platform Flash
PROM
TDI
TMS
TCK
CLK
CE
CEO
OE/RESET
CF⁽⁴⁾
BUSY⁽³⁾
GND
TDO
Platform Flash In-System Programmable Configuration PROMs
V_CCO(2)
(1)
D[0:7]
MODE PINS⁽¹⁾
RDWR_B
CS_B
Xilinx FPGA
Slave SelectMAP
CCLK
DONE
INIT_B
PROG_B
BUSY⁽³⁾
TDI
TMS
TCK
TDO
GND
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY⁽³⁾
Optional slave
FPGAs with
identical
configurations
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet or FPGA family
configuration user guide.
2 For compatible voltages, refer to the appropriate data sheet.
3 The BUSY pin is only available with the XCFxxP Platform Flash PROM (only certain FPGA families require the BUSY
pin connection for high-frequency SelectMAP mode configuration). For FPGAs that do not have a BUSY pin or do not
use their BUSY pin during configuration, the Platform Flash PROM BUSY pin should be unconnected or grounded.
For BUSY pin requirements, refer to the appropriate FPGA data sheet or FPGA family configuration user guide.
4 For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP, if CF is not connected to PROG_B, then it must be
tied to V_CCO via a 4.7 kΩ pull-up resistor.
Figure 10: Configuring in Slave SelectMAP Mode
ds123_15_110707
DS123 (v2.13.1) April 3, 2008
www.xilinx.com
Product Specification
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